Commit f5d07956 authored by Jessica Zhang's avatar Jessica Zhang Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Fix adjusted mode clock check for 3d merge 



Since 3D merge allows for larger modes to be supported across 2 layer
mixers, filter modes based on adjusted mode clock / 2 when 3d merge is
supported.

Reported-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Fixes: 62b7d683 ("drm/msm/dpu: Filter modes based on adjusted mode clock")
Signed-off-by: default avatarJessica Zhang <jessica.zhang@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Tested-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Tested-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/676353/
Link: https://lore.kernel.org/r/20250923-modeclk-fix-v2-1-01fcd0b2465a@oss.qualcomm.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent bbc65d1b

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

+3 −0
Original line number Diff line number Diff line
@@ -1545,6 +1545,9 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc, 
	adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock,

							    dpu_kms->perf.perf_cfg);



	if (dpu_kms->catalog->caps->has_3d_merge)

		adjusted_mode_clk /= 2;



	/*

	 * The given mode, adjusted for the perf clock factor, should not exceed

	 * the max core clock rate