Commit f5d4233a authored by Yong Wu's avatar Yong Wu Committed by Joerg Roedel
Browse files

iommu/mediatek: mt8186: Add iova_region_larb_msk 



Add iova_region_larb_msk for mt8186. We separate the 16GB iova regions
by each device's larbid/portid.
Note: larb5/6/10/12/14/15/18 connect nothing in this SoC.
Refer to include/dt-bindings/memory/mt8186-memory-port.h

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230411093144.2690-8-yong.wu@mediatek.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent a43e767d

drivers/iommu/mtk_iommu.c

+13 −0
Original line number Diff line number Diff line
@@ -1533,6 +1533,18 @@ static const struct mtk_iommu_plat_data mt8183_data = { 
	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},

};



static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {

	[0] = {~0, ~0, ~0},			/* Region0: all ports for larb0/1/2 */

	[1] = {0, 0, 0, 0, ~0, 0, 0, ~0},	/* Region1: larb4/7 */

	[2] = {0, 0, 0, 0, 0, 0, 0, 0,		/* Region2: larb8/9/11/13/16/17/19/20 */

	       ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0,

						/* larb13: the other ports except port9/10 */

	       ~0, ~0, 0, ~0, ~0},

	[3] = {0},

	[4] = {[13] = BIT(9) | BIT(10)},	/* larb13 port9/10 */

	[5] = {[14] = ~0},			/* larb14 */

};



static const struct mtk_iommu_plat_data mt8186_data_mm = {

	.m4u_plat       = M4U_MT8186,

	.flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
@@ -1545,6 +1557,7 @@ static const struct mtk_iommu_plat_data mt8186_data_mm = { 
	.banks_enable   = {true},

	.iova_region    = mt8192_multi_dom,

	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),

	.iova_region_larb_msk = mt8186_larb_region_msk,

};



static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {