Commit f5f1a977 authored Jun 02, 2022 by Sibi Sankar Committed by Rob Herring Jun 02, 2022

dt-bindings: Update Sibi Sankar's email address



Update email address to the quicinc.com domain.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1654130923-18722-1-git-send-email-quic_sibis@quicinc.com

parent 304e4d53

Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml

+1 −1

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		@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
		title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider

		maintainers:
		- Sibi Sankar <sibis@codeaurora.org>
		- Sibi Sankar <quic_sibis@quicinc.com>

		description:
		L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.

Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml

+1 −1

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		@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
		title: Qualcomm AOSS Reset Controller

		maintainers:
		- Sibi Sankar <sibis@codeaurora.org>
		- Sibi Sankar <quic_sibis@quicinc.com>

		description:
		The bindings describe the reset-controller found on AOSS-CC (always on

Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml

+1 −1

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		@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
		title: Qualcomm PDC Global

		maintainers:
		- Sibi Sankar <sibis@codeaurora.org>
		- Sibi Sankar <quic_sibis@quicinc.com>

		description:
		The bindings describes the reset-controller found on PDC-Global (Power Domain