Commit f5f2e20b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.18-1-2025-11-06' of... 

Merge tag 'perf-tools-fixes-for-v6.18-1-2025-11-06' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools fixes from Arnaldo Carvalho de Melo:

 - Add James Clark as a perf tools reviewer

 - Handle '1' type symbols in /proc/kallsyms, related to anonymous
   Rust closures in the DRM panic QR encoder, caught by 'perf test'

 - Sync kernel header copies: MSRs, uprobe syscall,
   DRM_IOCTL_GEM_CHANGE_HANDLE, KVM exit reasons, etc

* tag 'perf-tools-fixes-for-v6.18-1-2025-11-06' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools:
  perf symbols: Handle '1' symbols in /proc/kallsyms
  tools headers asm: Sync fls headers header with the kernel sources
  tools headers UAPI: Sync KVM's vmx.h header with the kernel sources to handle new exit reasons
  tools headers svm: Sync svm headers with the kernel sources
  tools headers UAPI: Sync x86's asm/kvm.h with the kernel sources
  MAINTAINERS: Add James Clark as a perf tools reviewer
  tools headers UAPI: Sync linux/kvm.h with the kernel sources
  tools headers UAPI: Update tools's copy of drm.h to pick DRM_IOCTL_GEM_CHANGE_HANDLE
  tools headers x86 cpufeatures: Sync with the kernel sources
  tools headers x86: Sync table due to introducion of uprobe syscall
  tools headers: Sync uapi/linux/fcntl.h with the kernel sources
  tools headers: Sync uapi/linux/prctl.h with the kernel source
  tools headers uapi: Update fs.h with the kernel sources
  tools arch x86: Sync msr-index.h to pick AMD64_{PERF_CNTR_GLOBAL_STATUS_SET,SAVIC_CONTROL}, IA32_L3_QOS_{ABMC,EXT}_CFG
parents 225a97d6 7f17ef0d

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -20163,6 +20163,7 @@ R: Alexander Shishkin <alexander.shishkin@linux.intel.com> 
R:	Jiri Olsa <jolsa@kernel.org>

R:	Ian Rogers <irogers@google.com>

R:	Adrian Hunter <adrian.hunter@intel.com>

R:	James Clark <james.clark@linaro.org>

L:	linux-perf-users@vger.kernel.org

L:	linux-kernel@vger.kernel.org

S:	Supported

tools/arch/x86/include/asm/cpufeatures.h

+5 −0
Original line number Diff line number Diff line
@@ -444,6 +444,7 @@ 
#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* VM Page Flush MSR is supported */

#define X86_FEATURE_SEV_ES		(19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */

#define X86_FEATURE_SEV_SNP		(19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */

#define X86_FEATURE_SNP_SECURE_TSC	(19*32+ 8) /* SEV-SNP Secure TSC */

#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */

#define X86_FEATURE_SME_COHERENT	(19*32+10) /* hardware-enforced cache coherency */

#define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
@@ -495,6 +496,9 @@ 
#define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */

#define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */

#define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */

#define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */

#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */

#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */



/*

 * BUG word(s)
@@ -551,4 +555,5 @@ 
#define X86_BUG_ITS			X86_BUG( 1*32+ 7) /* "its" CPU is affected by Indirect Target Selection */

#define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 8) /* "its_native_only" CPU is affected by ITS, VMX is not affected */

#define X86_BUG_TSA			X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transient Scheduler Attacks */

#define X86_BUG_VMSCAPE			X86_BUG( 1*32+10) /* "vmscape" CPU is affected by VMSCAPE attacks from guests */

#endif /* _ASM_X86_CPUFEATURES_H */

tools/arch/x86/include/asm/msr-index.h

+19 −1
Original line number Diff line number Diff line
@@ -315,9 +315,12 @@ 
#define PERF_CAP_PT_IDX			16



#define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6



#define PERF_CAP_LBR_FMT		0x3f

#define PERF_CAP_PEBS_TRAP		BIT_ULL(6)

#define PERF_CAP_ARCH_REG		BIT_ULL(7)

#define PERF_CAP_PEBS_FORMAT		0xf00

#define PERF_CAP_FW_WRITES		BIT_ULL(13)

#define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)

#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)

#define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
@@ -633,6 +636,11 @@ 
#define MSR_AMD_PPIN			0xc00102f1

#define MSR_AMD64_CPUID_FN_7		0xc0011002

#define MSR_AMD64_CPUID_FN_1		0xc0011004



#define MSR_AMD64_CPUID_EXT_FEAT	0xc0011005

#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT	54

#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT	BIT_ULL(MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT)



#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_DC_CFG		0xc0011022

#define MSR_AMD64_TW_CFG		0xc0011023
@@ -701,8 +709,15 @@ 
#define MSR_AMD64_SNP_VMSA_REG_PROT	BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)

#define MSR_AMD64_SNP_SMT_PROT_BIT	17

#define MSR_AMD64_SNP_SMT_PROT		BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)

#define MSR_AMD64_SNP_RESV_BIT		18

#define MSR_AMD64_SNP_SECURE_AVIC_BIT	18

#define MSR_AMD64_SNP_SECURE_AVIC	BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT)

#define MSR_AMD64_SNP_RESV_BIT		19

#define MSR_AMD64_SNP_RESERVED_MASK	GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)

#define MSR_AMD64_SAVIC_CONTROL		0xc0010138

#define MSR_AMD64_SAVIC_EN_BIT		0

#define MSR_AMD64_SAVIC_EN		BIT_ULL(MSR_AMD64_SAVIC_EN_BIT)

#define MSR_AMD64_SAVIC_ALLOWEDNMI_BIT	1

#define MSR_AMD64_SAVIC_ALLOWEDNMI	BIT_ULL(MSR_AMD64_SAVIC_ALLOWEDNMI_BIT)

#define MSR_AMD64_RMP_BASE		0xc0010132

#define MSR_AMD64_RMP_END		0xc0010133

#define MSR_AMD64_RMP_CFG		0xc0010136
@@ -735,6 +750,7 @@ 
#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300

#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301

#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302

#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET	0xc0000303



/* AMD Hardware Feedback Support MSRs */

#define MSR_AMD_WORKLOAD_CLASS_CONFIG		0xc0000500
@@ -1225,6 +1241,8 @@ 
/* - AMD: */

#define MSR_IA32_MBA_BW_BASE		0xc0000200

#define MSR_IA32_SMBA_BW_BASE		0xc0000280

#define MSR_IA32_L3_QOS_ABMC_CFG	0xc00003fd

#define MSR_IA32_L3_QOS_EXT_CFG		0xc00003ff

#define MSR_IA32_EVT_CFG_BASE		0xc0000400



/* AMD-V MSRs */

tools/arch/x86/include/uapi/asm/kvm.h

+34 −0
Original line number Diff line number Diff line
@@ -35,6 +35,11 @@ 
#define MC_VECTOR 18

#define XM_VECTOR 19

#define VE_VECTOR 20

#define CP_VECTOR 21



#define HV_VECTOR 28

#define VC_VECTOR 29

#define SX_VECTOR 30



/* Select x86 specific features in <linux/kvm.h> */

#define __KVM_HAVE_PIT
@@ -411,6 +416,35 @@ struct kvm_xcrs { 
	__u64 padding[16];

};



#define KVM_X86_REG_TYPE_MSR		2

#define KVM_X86_REG_TYPE_KVM		3



#define KVM_X86_KVM_REG_SIZE(reg)						\

({										\

	reg == KVM_REG_GUEST_SSP ? KVM_REG_SIZE_U64 : 0;			\

})



#define KVM_X86_REG_TYPE_SIZE(type, reg)					\

({										\

	__u64 type_size = (__u64)type << 32;					\

										\

	type_size |= type == KVM_X86_REG_TYPE_MSR ? KVM_REG_SIZE_U64 :		\

		     type == KVM_X86_REG_TYPE_KVM ? KVM_X86_KVM_REG_SIZE(reg) :	\

		     0;								\

	type_size;								\

})



#define KVM_X86_REG_ID(type, index)				\

	(KVM_REG_X86 | KVM_X86_REG_TYPE_SIZE(type, index) | index)



#define KVM_X86_REG_MSR(index)					\

	KVM_X86_REG_ID(KVM_X86_REG_TYPE_MSR, index)

#define KVM_X86_REG_KVM(index)					\

	KVM_X86_REG_ID(KVM_X86_REG_TYPE_KVM, index)



/* KVM-defined registers starting from 0 */

#define KVM_REG_GUEST_SSP	0



#define KVM_SYNC_X86_REGS      (1UL << 0)

#define KVM_SYNC_X86_SREGS     (1UL << 1)

#define KVM_SYNC_X86_EVENTS    (1UL << 2)

tools/arch/x86/include/uapi/asm/svm.h

+4 −0
Original line number Diff line number Diff line
@@ -118,6 +118,10 @@ 
#define SVM_VMGEXIT_AP_CREATE			1

#define SVM_VMGEXIT_AP_DESTROY			2

#define SVM_VMGEXIT_SNP_RUN_VMPL		0x80000018

#define SVM_VMGEXIT_SAVIC			0x8000001a

#define SVM_VMGEXIT_SAVIC_REGISTER_GPA		0

#define SVM_VMGEXIT_SAVIC_UNREGISTER_GPA	1

#define SVM_VMGEXIT_SAVIC_SELF_GPA		~0ULL

#define SVM_VMGEXIT_HV_FEATURES			0x8000fffd

#define SVM_VMGEXIT_TERM_REQUEST		0x8000fffe

#define SVM_VMGEXIT_TERM_REASON(reason_set, reason_code)	\