Commit f63ea193 authored by Shawn Lin's avatar Shawn Lin Committed by Heiko Stuebner
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arm64: dts: rockchip: Fix rk356x PCIe range mappings 



The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
that there is no same address allocated from normal system memory. Otherwise
it's broken if the same address assigned to the EP for DMA purpose.Fix it to
sync with the vendor BSP.

Fixes: 568a67e7 ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings")
Fixes: 66b51ea7 ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
Cc: stable@vger.kernel.org
Cc: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1767600929-195341-1-git-send-email-shawn.lin@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 9e3f8ae0

arch/arm64/boot/dts/rockchip/rk3568.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -185,7 +185,7 @@ pcie3x1: pcie@fe270000 { 
		      <0x0 0xf2000000 0x0 0x00100000>;

		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,

			 <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;

			 <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;

		reg-names = "dbi", "apb", "config";

		resets = <&cru SRST_PCIE30X1_POWERUP>;

		reset-names = "pipe";
@@ -238,7 +238,7 @@ pcie3x2: pcie@fe280000 { 
		      <0x0 0xf0000000 0x0 0x00100000>;

		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,

			 <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;

			 <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;

		reg-names = "dbi", "apb", "config";

		resets = <&cru SRST_PCIE30X2_POWERUP>;

		reset-names = "pipe";

arch/arm64/boot/dts/rockchip/rk356x-base.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1022,7 +1022,7 @@ pcie2x1: pcie@fe260000 { 
		power-domains = <&power RK3568_PD_PIPE>;

		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,

			 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;

			 <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;

		resets = <&cru SRST_PCIE20_POWERUP>;

		reset-names = "pipe";

		#address-cells = <3>;