Commit f70a68bc authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: convert vlv_dpio_read()/write() from pipe to phy 



vlv_dpio_read() and vlv_dpio_write() really operate on the phy, not
pipe. Passing the pipe instead of the phy as parameter is supposed to be
a convenience, but when the caller has the phy, it becomes an
inconvenience. See e.g. chv_dpio_cmn_power_well_enable() and
assert_chv_phy_powergate().

Figure out the phy in the callers, and pass phy to the dpio functions.

v2: retract one overzealous pipe->phy change (Ville)

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231114104534.4180144-3-jani.nikula@intel.com
parent 9fda18c2

drivers/gpu/drm/i915/display/intel_display_power_well.c

+9 −14
Original line number Diff line number Diff line
@@ -1400,20 +1400,16 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 
{

	enum i915_power_well_id id = i915_power_well_instance(power_well)->id;

	enum dpio_phy phy;

	enum pipe pipe;

	u32 tmp;



	drm_WARN_ON_ONCE(&dev_priv->drm,

			 id != VLV_DISP_PW_DPIO_CMN_BC &&

			 id != CHV_DISP_PW_DPIO_CMN_D);



	if (id == VLV_DISP_PW_DPIO_CMN_BC) {

		pipe = PIPE_A;

	if (id == VLV_DISP_PW_DPIO_CMN_BC)

		phy = DPIO_PHY0;

	} else {

		pipe = PIPE_C;

	else

		phy = DPIO_PHY1;

	}



	/* since ref/cri clock was enabled */

	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
@@ -1428,24 +1424,24 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 
	vlv_dpio_get(dev_priv);



	/* Enable dynamic power down */

	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);

	tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW28);

	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |

		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);

	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp);



	if (id == VLV_DISP_PW_DPIO_CMN_BC) {

		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);

		tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1);

		tmp |= DPIO_DYNPWRDOWNEN_CH1;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);

		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp);

	} else {

		/*

		 * Force the non-existing CL2 off. BXT does this

		 * too, so maybe it saves some power even though

		 * CL2 doesn't exist?

		 */

		tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);

		tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW30);

		tmp |= DPIO_CL2_LDOFUSE_PWRENB;

		vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);

		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW30, tmp);

	}



	vlv_dpio_put(dev_priv);
@@ -1499,7 +1495,6 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 
static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,

				     enum dpio_channel ch, bool override, unsigned int mask)

{

	enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;

	u32 reg, val, expected, actual;



	/*
@@ -1518,7 +1513,7 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi 
		reg = _CHV_CMN_DW6_CH1;



	vlv_dpio_get(dev_priv);

	val = vlv_dpio_read(dev_priv, pipe, reg);

	val = vlv_dpio_read(dev_priv, phy, reg);

	vlv_dpio_put(dev_priv);



	/*

drivers/gpu/drm/i915/display/intel_dpio_phy.c

+80 −77
Original line number Diff line number Diff line
@@ -703,50 +703,50 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, 
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);

	enum pipe pipe = crtc->pipe;

	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

	u32 val;

	int i;



	vlv_dpio_get(dev_priv);



	/* Clear calc init */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));

	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);

	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);

	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));

		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);

		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);

		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);

	}



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch));

	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);

	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch));

		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);

		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val);

	}



	/* Program swing deemph */

	for (i = 0; i < crtc_state->lane_count; i++) {

		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));

		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i));

		val &= ~DPIO_SWING_DEEMPH9P5_MASK;

		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;

		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);

		vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val);

	}



	/* Program swing margin */

	for (i = 0; i < crtc_state->lane_count; i++) {

		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));

		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i));



		val &= ~DPIO_SWING_MARGIN000_MASK;

		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
@@ -759,7 +759,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, 
		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);

		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;



		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);

		vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val);

	}



	/*
@@ -769,23 +769,23 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, 
	 * 27 for ch0 and ch1.

	 */

	for (i = 0; i < crtc_state->lane_count; i++) {

		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));

		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i));

		if (uniq_trans_scale)

			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;

		else

			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;

		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);

		vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val);

	}



	/* Start swing calculation */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));

	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));

		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);

	}



	vlv_dpio_put(dev_priv);
@@ -796,43 +796,43 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, 
			      bool reset)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum pipe pipe = crtc->pipe;

	enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));

	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

	u32 val;



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));

	if (reset)

		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

	else

		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch));

		if (reset)

			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

		else

			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val);

	}



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch));

	val |= CHV_PCS_REQ_SOFTRESET_EN;

	if (reset)

		val &= ~DPIO_PCS_CLK_SOFT_RESET;

	else

		val |= DPIO_PCS_CLK_SOFT_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch));

		val |= CHV_PCS_REQ_SOFTRESET_EN;

		if (reset)

			val &= ~DPIO_PCS_CLK_SOFT_RESET;

		else

			val |= DPIO_PCS_CLK_SOFT_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val);

	}

}
@@ -843,6 +843,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);

	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

	enum pipe pipe = crtc->pipe;

	unsigned int lane_mask =

		intel_dp_unused_lane_mask(crtc_state->lane_count);
@@ -865,40 +866,40 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 


	/* program left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA1_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA1_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA2_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA2_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);

	}



	/* program clock channel usage */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch));

	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

	if (pipe != PIPE_B)

		val &= ~CHV_PCS_USEDCLKCHANNEL;

	else

		val |= CHV_PCS_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch));

		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

		if (pipe != PIPE_B)

			val &= ~CHV_PCS_USEDCLKCHANNEL;

		else

			val |= CHV_PCS_USEDCLKCHANNEL;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val);

	}



	/*
@@ -906,12 +907,12 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 
	 * matches the pipe, but here we need to

	 * pick the CL based on the port.

	 */

	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));

	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch));

	if (pipe != PIPE_B)

		val &= ~CHV_CMN_USEDCLKCHANNEL;

	else

		val |= CHV_CMN_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val);



	vlv_dpio_put(dev_priv);

}
@@ -924,21 +925,21 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);

	enum pipe pipe = crtc->pipe;

	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

	int data, i, stagger;

	u32 val;



	vlv_dpio_get(dev_priv);



	/* allow hardware to manage TX FIFO reset source */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));

	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));

		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);

	}



	/* Program Tx lane latency optimal setting*/
@@ -948,7 +949,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
			data = 0x0;

		else

			data = (i == 1) ? 0x0 : 0x1;

		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),

		vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i),

				data << DPIO_UPAR_SHIFT);

	}
@@ -964,17 +965,17 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
	else

		stagger = 0x2;



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));

	val |= DPIO_TX2_STAGGER_MASK(0x1f);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);



	if (crtc_state->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));

		val |= DPIO_TX2_STAGGER_MASK(0x1f);

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);

	}



	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),

	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch),

		       DPIO_LANESTAGGER_STRAP(stagger) |

		       DPIO_LANESTAGGER_STRAP_OVRD |

		       DPIO_TX1_STAGGER_MASK(0x1f) |
@@ -982,7 +983,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
		       DPIO_TX2_STAGGER_MULT(0));



	if (crtc_state->lane_count > 2) {

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),

		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch),

			       DPIO_LANESTAGGER_STRAP(stagger) |

			       DPIO_LANESTAGGER_STRAP_OVRD |

			       DPIO_TX1_STAGGER_MASK(0x1f) |
@@ -1012,19 +1013,20 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;

	enum dpio_phy phy = vlv_pipe_to_phy(pipe);

	u32 val;



	vlv_dpio_get(dev_priv);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);

	}



	vlv_dpio_put(dev_priv);
@@ -1050,22 +1052,22 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, 
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);

	enum pipe pipe = crtc->pipe;

	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);



	vlv_dpio_get(dev_priv);



	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),

	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x00000000);

	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);

	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),

			 uniqtranscale_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);

	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);



	if (tx3_demph)

		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);

		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);



	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x00030000);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);

	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);



	vlv_dpio_put(dev_priv);

}
@@ -1077,24 +1079,24 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);

	enum pipe pipe = crtc->pipe;

	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);



	/* Program Tx lane resets to default */

	vlv_dpio_get(dev_priv);



	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),

			 DPIO_PCS_TX_LANE2_RESET |

			 DPIO_PCS_TX_LANE1_RESET);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),

			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |

			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |

			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |

				 DPIO_PCS_CLK_SOFT_RESET);



	/* Fix up inter-pair skew failure */

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00);

	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x00001500);

	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x40400000);



	vlv_dpio_put(dev_priv);

}
@@ -1108,23 +1110,24 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);

	enum pipe pipe = crtc->pipe;

	enum dpio_phy phy = vlv_pipe_to_phy(pipe);

	u32 val;



	vlv_dpio_get(dev_priv);



	/* Enable clock channels for this port */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));

	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port));

	val = 0;

	if (pipe)

		val |= (1<<21);

	else

		val &= ~(1<<21);

	val |= 0x001000c4;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);



	/* Program lane clock */

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888);



	vlv_dpio_put(dev_priv);

}
@@ -1136,10 +1139,10 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);

	enum pipe pipe = crtc->pipe;

	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);



	vlv_dpio_get(dev_priv);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x00000000);

	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), 0x00e00060);

	vlv_dpio_put(dev_priv);

}

drivers/gpu/drm/i915/display/intel_dpll.c

+55 −51

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/vlv_sideband.c

+4 −6
Original line number Diff line number Diff line
@@ -227,9 +227,8 @@ static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy p 
		return IOSF_PORT_DPIO;

}



u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)

u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg)

{

	enum dpio_phy phy = vlv_pipe_to_phy(pipe);

	u32 port = vlv_dpio_phy_iosf_port(i915, phy);

	u32 val = 0;
@@ -240,16 +239,15 @@ u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg) 
	 * so ideally we should check the register offset instead...

	 */

	drm_WARN(&i915->drm, val == 0xffffffff,

		 "DPIO read pipe %c reg 0x%x == 0x%x\n",

		 pipe_name(pipe), reg, val);

		 "DPIO PHY%d read reg 0x%x == 0x%x\n",

		 phy, reg, val);



	return val;

}



void vlv_dpio_write(struct drm_i915_private *i915,

		    enum pipe pipe, int reg, u32 val)

		    enum dpio_phy phy, int reg, u32 val)

{

	enum dpio_phy phy = vlv_pipe_to_phy(pipe);

	u32 port = vlv_dpio_phy_iosf_port(i915, phy);



	vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);

drivers/gpu/drm/i915/vlv_sideband.h

+3 −3
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 


#include "vlv_sideband_reg.h"



enum pipe;

enum dpio_phy;

struct drm_i915_private;



enum {
@@ -75,9 +75,9 @@ static inline void vlv_dpio_get(struct drm_i915_private *i915) 
	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));

}



u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);

u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg);

void vlv_dpio_write(struct drm_i915_private *i915,

		    enum pipe pipe, int reg, u32 val);

		    enum dpio_phy phy, int reg, u32 val);



static inline void vlv_dpio_put(struct drm_i915_private *i915)

{