Commit f72e2559 authored by Jijie Shao's avatar Jijie Shao Committed by Paolo Abeni
Browse files

net: hibmcge: Implement rx_poll function to receive packets 



Implement rx_poll function to read the rx descriptor after
receiving the rx interrupt. Adjust the skb based on the
descriptor to complete the reception of the packet.

Signed-off-by: default avatarJijie Shao <shaojijie@huawei.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 40735e75

drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h

+5 −0
Original line number Diff line number Diff line
@@ -15,6 +15,10 @@ 
#define HBG_VECTOR_NUM			4

#define HBG_PCU_CACHE_LINE_SIZE		32

#define HBG_TX_TIMEOUT_BUF_LEN		1024

#define HBG_RX_DESCR			0x01



#define HBG_PACKET_HEAD_SIZE	((HBG_RX_SKIP1 + HBG_RX_SKIP2 + \

				  HBG_RX_DESCR) * HBG_PCU_CACHE_LINE_SIZE)



enum hbg_dir {

	HBG_DIR_TX = 1 << 0,
@@ -121,6 +125,7 @@ struct hbg_priv { 
	struct hbg_mac mac;

	struct hbg_vector vectors;

	struct hbg_ring tx_ring;

	struct hbg_ring rx_ring;

};



#endif

drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c

+10 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ static int hbg_hw_dev_specs_init(struct hbg_priv *priv) 
		return -EADDRNOTAVAIL;



	specs->max_frame_len = HBG_PCU_CACHE_LINE_SIZE + specs->max_mtu;

	specs->rx_buf_size = HBG_PACKET_HEAD_SIZE + specs->max_frame_len;

	return 0;

}
@@ -178,6 +179,10 @@ u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir) 
		return hbg_reg_read_field(priv, HBG_REG_CF_CFF_DATA_NUM_ADDR,

					  HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M);



	if (dir & HBG_DIR_RX)

		return hbg_reg_read_field(priv, HBG_REG_CF_CFF_DATA_NUM_ADDR,

					  HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M);



	return 0;

}
@@ -189,6 +194,11 @@ void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc) 
	hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_3_ADDR, tx_desc->word3);

}



void hbg_hw_fill_buffer(struct hbg_priv *priv, u32 buffer_dma_addr)

{

	hbg_reg_write(priv, HBG_REG_RX_CFF_ADDR_ADDR, buffer_dma_addr);

}



void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex)

{

	hbg_reg_write_field(priv, HBG_REG_PORT_MODE_ADDR,

drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h

+1 −0
Original line number Diff line number Diff line
@@ -54,5 +54,6 @@ void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable); 
void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr);

u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir);

void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc);

void hbg_hw_fill_buffer(struct hbg_priv *priv, u32 buffer_dma_addr);



#endif

drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c

+7 −1
Original line number Diff line number Diff line
@@ -19,13 +19,19 @@ static void hbg_irq_handle_tx(struct hbg_priv *priv, 
	napi_schedule(&priv->tx_ring.napi);

}



static void hbg_irq_handle_rx(struct hbg_priv *priv,

			      struct hbg_irq_info *irq_info)

{

	napi_schedule(&priv->rx_ring.napi);

}



#define HBG_TXRX_IRQ_I(name, handle) \

	{#name, HBG_INT_MSK_##name##_B, false, false, 0, handle}

#define HBG_ERR_IRQ_I(name, need_print) \

	{#name, HBG_INT_MSK_##name##_B, true, need_print, 0, hbg_irq_handle_err}



static struct hbg_irq_info hbg_irqs[] = {

	HBG_TXRX_IRQ_I(RX, NULL),

	HBG_TXRX_IRQ_I(RX, hbg_irq_handle_rx),

	HBG_TXRX_IRQ_I(TX, hbg_irq_handle_tx),

	HBG_ERR_IRQ_I(MAC_MII_FIFO_ERR, true),

	HBG_ERR_IRQ_I(MAC_PCS_RX_FIFO_ERR, true),

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

+13 −0
Original line number Diff line number Diff line
@@ -82,10 +82,12 @@ 
#define HBG_REG_MAX_FRAME_LEN_M			GENMASK(15, 0)

#define HBG_REG_CF_CFF_DATA_NUM_ADDR		(HBG_REG_SGMII_BASE + 0x045C)

#define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M	GENMASK(8, 0)

#define HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M	GENMASK(24, 16)

#define HBG_REG_TX_CFF_ADDR_0_ADDR		(HBG_REG_SGMII_BASE + 0x0488)

#define HBG_REG_TX_CFF_ADDR_1_ADDR		(HBG_REG_SGMII_BASE + 0x048C)

#define HBG_REG_TX_CFF_ADDR_2_ADDR		(HBG_REG_SGMII_BASE + 0x0490)

#define HBG_REG_TX_CFF_ADDR_3_ADDR		(HBG_REG_SGMII_BASE + 0x0494)

#define HBG_REG_RX_CFF_ADDR_ADDR		(HBG_REG_SGMII_BASE + 0x04A0)

#define HBG_REG_RX_BUF_SIZE_ADDR		(HBG_REG_SGMII_BASE + 0x04E4)

#define HBG_REG_RX_BUF_SIZE_M			GENMASK(15, 0)

#define HBG_REG_BUS_CTRL_ADDR			(HBG_REG_SGMII_BASE + 0x04E8)
@@ -127,4 +129,15 @@ struct hbg_tx_desc { 
#define HBG_TX_DESC_W0_l4_CS_B		BIT(0)

#define HBG_TX_DESC_W1_SEND_LEN_M	GENMASK(19, 4)



struct hbg_rx_desc {

	u32 word0;

	u32 word1; /* tag */

	u32 word2;

	u32 word3;

	u32 word4;

	u32 word5;

};



#define HBG_RX_DESC_W2_PKT_LEN_M	GENMASK(31, 16)



#endif