Commit f7c79949 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-7.1-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Paul Walmsley:
 "Relatively low-impact fixes. Probably the most notable one is that we
  no longer ask the monitor-mode firmware to delegate misaligned access
  handling to the kernel by default, since the kernel code needs
  significant improvement to match the functionality of the firmware.
  This change avoids functional problems at some cost in performance,
  but shouldn't affect any system with misaligned access handling in
  hardware.

   - Disable satp register probing when no5lvl is specified on the
     kernel command line

   - Fix a CFI-related issue with the misaligned access speed
     measurement code

   - Reduce the CFI shadow stack size limit from 4GB to 2GB (following
     ARM64 GCS)

   - Prevent the kernel from requesting delegation of misaligned access
     faults unless a new Kconfig option, RISCV_SBI_FWFT_DELEGATE_MISALIGNED,
     is enabled. This will depend on CONFIG_NONPORTABLE until the
     deficiencies of the kernel misaligned access fixup code are fixed

   - Fix some potential uninitialized memory accesses in error paths in
     compat_riscv_gpr_set() and compat_restore_sigcontext()

   - Fix a bug in the RISC-V MIPS vendor errata patching code where a
     logical-and was used in place of a bitwise-and

   - Drop some unnecessary code in riscv_fill_hwcap_from_isa_string()

   - Use macros for isa2hwcap indices in riscv_fill_hwcap(), rather than
     open-coding them

   - Fix some documentation typos (one affecting 'make htmldocs')"

* tag 'riscv-for-linus-7.1-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: misaligned: Make enabling delegation depend on NONPORTABLE
  riscv: Docs: fix unmatched quote warning
  riscv: cfi: reduce shadow stack size limit from 4GB to 2GB
  riscv: cpufeature: Use pre-defined ISA ext macros to index isa2hwcap
  riscv: mm: Fixup no5lvl failure when vaddr is invalid
  riscv: Fix register corruption from uninitialized cregs on error
  riscv: errata: Fix bitwise vs logical AND in MIPS errata patching
  Documentation: riscv: cmodx: fix typos
  riscv: cpufeature: Drop this_hwcap clear in T-Head vector workaround
  riscv: Define __riscv_copy_{,vec_}{words,bytes}_unaligned() using SYM_TYPED_FUNC_START
parents 1405a071 b69bcb13

Documentation/arch/riscv/cmodx.rst

+4 −4
Original line number Diff line number Diff line
@@ -21,13 +21,13 @@ call at each patchable function entry, and patches it dynamically at runtime to 
enable or disable the redirection. In the case of RISC-V, 2 instructions,

AUIPC + JALR, are required to compose a function call. However, it is impossible

to patch 2 instructions and expect that a concurrent read-side executes them

without a race condition. This series makes atmoic code patching possible in

without a race condition. This series makes atomic code patching possible in

RISC-V ftrace. Kernel preemption makes things even worse as it allows the old

state to persist across the patching process with stop_machine().



In order to get rid of stop_machine() and run dynamic ftrace with full kernel

preemption, we partially initialize each patchable function entry at boot-time,

setting the first instruction to AUIPC, and the second to NOP. Now, atmoic

setting the first instruction to AUIPC, and the second to NOP. Now, atomic

patching is possible because the kernel only has to update one instruction.

According to Ziccif, as long as an instruction is naturally aligned, the ISA

guarantee an  atomic update.
@@ -36,8 +36,8 @@ By fixing down the first instruction, AUIPC, the range of the ftrace trampoline 
is limited to +-2K from the predetermined target, ftrace_caller, due to the lack

of immediate encoding space in RISC-V. To address the issue, we introduce

CALL_OPS, where an 8B naturally align metadata is added in front of each

pacthable function. The metadata is resolved at the first trampoline, then the

execution can be derect to another custom trampoline.

patchable function. The metadata is resolved at the first trampoline, then the

execution can be directed to another custom trampoline.



CMODX in the User Space

-----------------------

Documentation/arch/riscv/zicfilp.rst

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ the program. 


Per-task indirect branch tracking state can be monitored and

controlled via the :c:macro:`PR_GET_CFI` and :c:macro:`PR_SET_CFI`

``prctl()` arguments (respectively), by supplying

``prctl()`` arguments (respectively), by supplying

:c:macro:`PR_CFI_BRANCH_LANDING_PADS` as the second argument.  These

are architecture-agnostic, and will return -EINVAL if the underlying

functionality is not supported.

arch/riscv/Kconfig

+22 −0
Original line number Diff line number Diff line
@@ -937,6 +937,28 @@ config RISCV_VECTOR_MISALIGNED 
	help

	  Enable detecting support for vector misaligned loads and stores.



config RISCV_SBI_FWFT_DELEGATE_MISALIGNED

	bool "Request firmware delegation of unaligned access exceptions"

	depends on RISCV_SBI

	depends on NONPORTABLE

	help

	  Use SBI FWFT to request delegation of load address misaligned and

	  store address misaligned exceptions, if possible, and prefer Linux

	  kernel emulation of these accesses to firmware emulation.



	  Unfortunately, Linux's emulation is still incomplete. Namely, it

	  currently does not handle vector instructions and KVM guest accesses.

	  On platforms where these accesses would have been handled by firmware,

	  enabling this causes unexpected kernel oopses, userspaces crashes and

	  KVM guest crashes. If you are sure that these are not a problem for

	  your platform, you can say Y here, which may improve performance.



	  Saying N here will not worsen emulation support for unaligned accesses

	  even in the case where the firmware also has incomplete support. It

	  simply keeps the firmware's emulation enabled.



	  If you don't know what to do here, say N.



choice

	prompt "Unaligned Accesses Support"

	default RISCV_PROBE_UNALIGNED_ACCESS

arch/riscv/errata/mips/errata.c

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, 
		}



		tmp = (1U << alt->patch_id);

		if (cpu_req_errata && tmp) {

		if (cpu_req_errata & tmp) {

			mutex_lock(&text_mutex);

			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),

					  alt->alt_len);

arch/riscv/kernel/compat_signal.c

+2 −0
Original line number Diff line number Diff line
@@ -107,6 +107,8 @@ static long compat_restore_sigcontext(struct pt_regs *regs, 


	/* sc_regs is structured the same as the start of pt_regs */

	err = __copy_from_user(&cregs, &sc->sc_regs, sizeof(sc->sc_regs));

	if (unlikely(err))

		return err;



	cregs_to_regs(&cregs, regs);