Commit f83cec3b authored by Victor Skvortsov's avatar Victor Skvortsov Committed by Alex Deucher
Browse files

drm/amdgpu: Disable dpm_enabled flag while VF is in reset 



VFs do not perform HW fini/suspend in FLR, so the dpm_enabled
is incorrectly kept enabled. Add interface to disable it in
virt_pre_reset call.

v2: Made implementation generic for all asics
v3: Re-order conditionals so PP_MP1_STATE_FLR is only evaluated on VF

Signed-off-by: default avatarVictor Skvortsov <victor.skvortsov@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35c71522

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −4
Original line number Diff line number Diff line
@@ -5289,10 +5289,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 
	if (reset_context->reset_req_dev == adev)

		job = reset_context->job;



	if (amdgpu_sriov_vf(adev)) {

		/* stop the data exchange thread */

		amdgpu_virt_fini_data_exchange(adev);

	}

	if (amdgpu_sriov_vf(adev))

		amdgpu_virt_pre_reset(adev);



	amdgpu_fence_driver_isr_toggle(adev, true);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+8 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include "amdgpu.h"

#include "amdgpu_ras.h"

#include "amdgpu_reset.h"

#include "amdgpu_dpm.h"

#include "vi.h"

#include "soc15.h"

#include "nv.h"
@@ -849,6 +850,13 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad 
	return mode;

}



void amdgpu_virt_pre_reset(struct amdgpu_device *adev)

{

	/* stop the data exchange thread */

	amdgpu_virt_fini_data_exchange(adev);

	amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_FLR);

}



void amdgpu_virt_post_reset(struct amdgpu_device *adev)

{

	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) {

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+1 −0
Original line number Diff line number Diff line
@@ -376,6 +376,7 @@ u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 
		      u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);

bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,

			uint32_t ucode_id);

void amdgpu_virt_pre_reset(struct amdgpu_device *adev);

void amdgpu_virt_post_reset(struct amdgpu_device *adev);

bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);

bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,

drivers/gpu/drm/amd/include/kgd_pp_interface.h

+1 −0
Original line number Diff line number Diff line
@@ -218,6 +218,7 @@ enum pp_mp1_state { 
	PP_MP1_STATE_SHUTDOWN,

	PP_MP1_STATE_UNLOAD,

	PP_MP1_STATE_RESET,

	PP_MP1_STATE_FLR,

};



enum pp_df_cstate {

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

+5 −1
Original line number Diff line number Diff line
@@ -168,7 +168,11 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 
	int ret = 0;

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;



	if (pp_funcs && pp_funcs->set_mp1_state) {

	if (mp1_state == PP_MP1_STATE_FLR) {

		/* VF lost access to SMU */

		if (amdgpu_sriov_vf(adev))

			adev->pm.dpm_enabled = false;

	} else if (pp_funcs && pp_funcs->set_mp1_state) {

		mutex_lock(&adev->pm.mutex);



		ret = pp_funcs->set_mp1_state(