Commit f8613561 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-fix-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi fixes from Mark Brown:
 "A few fairly small fixes for v6.13, the most substatial one being
  disabling STIG mode for Cadence QSPI controllers on Altera SoCFPGA
  platforms since it doesn't work"

* tag 'spi-fix-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA.
  spi: rockchip: Fix PM runtime count on no-op cs
  spi: aspeed: Fix an error handling path in aspeed_spi_[read|write]_user()
parents 4e1b4861 25fb0e77

drivers/spi/spi-aspeed-smc.c

+6 −4
Original line number Diff line number Diff line
@@ -239,7 +239,7 @@ static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip, 


	ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);

	if (ret < 0)

		return ret;

		goto stop_user;



	if (op->dummy.buswidth && op->dummy.nbytes) {

		for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
@@ -249,8 +249,9 @@ static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip, 
	aspeed_spi_set_io_mode(chip, io_mode);



	aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);

stop_user:

	aspeed_spi_stop_user(chip);

	return 0;

	return ret;

}



static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
@@ -261,10 +262,11 @@ static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip, 
	aspeed_spi_start_user(chip);

	ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);

	if (ret < 0)

		return ret;

		goto stop_user;

	aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);

stop_user:

	aspeed_spi_stop_user(chip);

	return 0;

	return ret;

}



/* support for 1-1-1, 1-1-2 or 1-1-4 */

drivers/spi/spi-cadence-quadspi.c

+8 −2
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); 
#define CQSPI_SLOW_SRAM		BIT(4)

#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR	BIT(5)

#define CQSPI_RD_NO_IRQ			BIT(6)

#define CQSPI_DISABLE_STIG_MODE		BIT(7)



/* Capabilities */

#define CQSPI_SUPPORTS_OCTAL		BIT(0)
@@ -103,6 +104,7 @@ struct cqspi_st { 
	bool			apb_ahb_hazard;



	bool			is_jh7110; /* Flag for StarFive JH7110 SoC */

	bool			disable_stig_mode;



	const struct cqspi_driver_platdata *ddata;

};
@@ -1416,7 +1418,8 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 
	 * reads, prefer STIG mode for such small reads.

	 */

		if (!op->addr.nbytes ||

		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)

		    (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&

		     !cqspi->disable_stig_mode))

			return cqspi_command_read(f_pdata, op);



		return cqspi_read(f_pdata, op);
@@ -1880,6 +1883,8 @@ static int cqspi_probe(struct platform_device *pdev) 
			if (ret)

				goto probe_reset_failed;

		}

		if (ddata->quirks & CQSPI_DISABLE_STIG_MODE)

			cqspi->disable_stig_mode = true;



		if (of_device_is_compatible(pdev->dev.of_node,

					    "xlnx,versal-ospi-1.0")) {
@@ -2043,7 +2048,8 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = { 
static const struct cqspi_driver_platdata socfpga_qspi = {

	.quirks = CQSPI_DISABLE_DAC_MODE

			| CQSPI_NO_SUPPORT_WR_COMPLETION

			| CQSPI_SLOW_SRAM,

			| CQSPI_SLOW_SRAM

			| CQSPI_DISABLE_STIG_MODE,

};



static const struct cqspi_driver_platdata versal_ospi = {

drivers/spi/spi-rockchip.c

+14 −0
Original line number Diff line number Diff line
@@ -241,6 +241,20 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 
	struct spi_controller *ctlr = spi->controller;

	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);

	bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;

	bool cs_actual;



	/*

	 * SPI subsystem tries to avoid no-op calls that would break the PM

	 * refcount below. It can't however for the first time it is used.

	 * To detect this case we read it here and bail out early for no-ops.

	 */

	if (spi_get_csgpiod(spi, 0))

		cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 1);

	else

		cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) &

			       BIT(spi_get_chipselect(spi, 0)));

	if (unlikely(cs_actual == cs_asserted))

		return;



	if (cs_asserted) {

		/* Keep things powered as long as CS is asserted */