Commit f868cd25 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-11-16' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Final week of fixes, lots of small amdgpu fixes, some i915 and xe
  fixes, the nouveau changes fix a recent regression and some laptop
  panel black screens, then a couple of other misc ones.

  It's probably a little busier than I'd like, but each fix seems fine.

  amdgpu:
   - PSR fix
   - Panel replay fixes
   - DML fix
   - vblank power fix
   - Fix video caps
   - SMU 14.0 fix
   - GPUVM fix
   - MES 12 fix
   - APU carve out fix
   - DC vbios fix
   - NBIO fix

  i915:
   - Don't load GSC on ARL-H and ARL-U if too old FW
   - Avoid potential OOPS in enabling/disabling TV output

  xe:
   - Fix unlock on exec ioctl error path
   - Fix hibernation on LNL due to ggtt getting lost
   - Fix missing runtime PM in OA release

  bridge:
   - tc358768: Fix DSI command tx

  nouveau:
   - Fix GSP AUX error handling
   - dp: Handle retires for AUX CH transfers with GSP
   - fw: Sync DMA after setup

  panthor:
   - Fix partial BO mappings to GPU

  rockchip:
   - vop: Avoid null-ptr deref in plane-state check

  vmwgfx:
   - Avoid null-ptr deref in surface creation"

* tag 'drm-fixes-2024-11-16' of https://gitlab.freedesktop.org/drm/kernel: (27 commits)
  drm/bridge: tc358768: Fix DSI command tx
  drm/vmwgfx: avoid null_ptr_deref in vmw_framebuffer_surface_create_handle
  nouveau/dp: handle retries for AUX CH transfers with GSP.
  nouveau: handle EBUSY and EAGAIN for GSP aux errors.
  nouveau: fw: sync dma after setup is called.
  drm/xe/oa: Fix "Missing outer runtime PM protection" warning
  drm/xe: handle flat ccs during hibernation on igpu
  drm/xe: improve hibernation on igpu
  drm/xe: Restore system memory GGTT mappings
  drm/xe: Ensure all locks released in exec IOCTL
  drm/panthor: Fix handling of partial GPU mapping of BOs
  drm/amd: Fix initialization mistake for NBIO 7.7.0
  Revert "drm/amd/display: parse umc_info or vram_info based on ASIC"
  drm/amd/display: Fix failure to read vram info due to static BP_RESULT
  drm/amdgpu: enable GTT fallback handling for dGPUs only
  drm/i915: Grab intel_display from the encoder to avoid potential oopsies
  drm/i915/gsc: ARL-H and ARL-U need a newer GSC FW.
  drm/amdgpu/mes12: correct kiq unmap latency
  drm/amdgpu: fix check in gmc_v9_0_get_vm_pte()
  drm/amd/pm: print pp_dpm_mclk in ascending order on SMU v14.0.0
  ...
parents f5395732 21c1c6c7

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+2 −1
Original line number Diff line number Diff line
@@ -161,7 +161,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		 * When GTT is just an alternative to VRAM make sure that we

		 * only use it as fallback and still try to fill up VRAM first.

		 */

		if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)

		if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&

		    !(adev->flags & AMD_IS_APU))

			places[c].flags |= TTM_PL_FLAG_FALLBACK;

		c++;

	}

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+8 −5
Original line number Diff line number Diff line
@@ -1124,8 +1124,10 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 
					 uint64_t *flags)

{

	struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);

	bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;

	bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT);

	bool is_vram = bo->tbo.resource &&

		bo->tbo.resource->mem_type == TTM_PL_VRAM;

	bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |

				     AMDGPU_GEM_CREATE_EXT_COHERENT);

	bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;

	bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;

	struct amdgpu_vm *vm = mapping->bo_va->base.vm;
@@ -1133,6 +1135,8 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 
	bool snoop = false;

	bool is_local;



	dma_resv_assert_held(bo->tbo.base.resv);



	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(9, 4, 1):

	case IP_VERSION(9, 4, 2):
@@ -1251,9 +1255,8 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 
		*flags &= ~AMDGPU_PTE_VALID;

	}



	if (bo && bo->tbo.resource)

		gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo,

					     mapping, flags);

	if ((*flags & AMDGPU_PTE_VALID) && bo)

		gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags);

}



static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+1 −1
Original line number Diff line number Diff line
@@ -550,7 +550,7 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 
	mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;

	mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;

	mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;

	mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;

	mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;



	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

			&mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

+6 −0
Original line number Diff line number Diff line
@@ -247,6 +247,12 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev) 
	if (def != data)

		WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);



	switch (adev->ip_versions[NBIO_HWIP][0]) {

	case IP_VERSION(7, 7, 0):

		data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);

		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data);

		break;

	}

}



static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/nv.c

+6 −6
Original line number Diff line number Diff line
@@ -67,8 +67,8 @@ static const struct amd_ip_funcs nv_common_ip_funcs; 


/* Navi */

static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},

};



static const struct amdgpu_video_codecs nv_video_codecs_encode = {
@@ -94,8 +94,8 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = { 


/* Sienna Cichlid */

static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},

};



static const struct amdgpu_video_codecs sc_video_codecs_encode = {
@@ -136,8 +136,8 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = { 


/* SRIOV Sienna Cichlid, not const since data is controlled by host */

static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},

};



static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {