Commit f88192d2 authored by loanchen's avatar loanchen Committed by Alex Deucher
Browse files

drm/amd/display: Correct register address in dcn35 



[Why]
the offset address of mmCLK5_spll_field_8 was incorrect for dcn35
which causes SSC not to be enabled.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Signed-off-by: default avatarLo-An Chen <lo-an.chen@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 819bf666

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ 
#define mmCLK1_CLK4_ALLOW_DS 0x16EA8

#define mmCLK1_CLK5_ALLOW_DS 0x16EB1



#define mmCLK5_spll_field_8 0x1B04B

#define mmCLK5_spll_field_8 0x1B24B

#define mmDENTIST_DISPCLK_CNTL 0x0124

#define regDENTIST_DISPCLK_CNTL 0x0064

#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1