Commit f8a26528 authored by Kai Ye's avatar Kai Ye Committed by Herbert Xu
Browse files

crypto: hisilicon/sec - not need to enable sm4 extra mode at HW V3 



It is not need to enable sm4 extra mode in at HW V3. Here is fix it.

Signed-off-by: default avatarKai Ye <yekai13@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent aec01cc8

drivers/crypto/hisilicon/sec2/sec_main.c

+5 −3
Original line number Diff line number Diff line
@@ -472,9 +472,11 @@ static int sec_engine_init(struct hisi_qm *qm) 


	writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);



	/* Enable sm4 extra mode, as ctr/ecb */

	/* HW V2 enable sm4 extra mode, as ctr/ecb */

	if (qm->ver < QM_HW_V3)

		writel_relaxed(SEC_BD_ERR_CHK_EN0,

			       qm->io_base + SEC_BD_ERR_CHK_EN_REG0);



	/* Enable sm4 xts mode multiple iv */

	writel_relaxed(SEC_BD_ERR_CHK_EN1,

		       qm->io_base + SEC_BD_ERR_CHK_EN_REG1);