Unverified Commit f8c91d96 authored by Apoorva Singh's avatar Apoorva Singh Committed by Rodrigo Vivi
Browse files

drm/xe/xe3lpg: Add Wa_16024792527 



Force Sampler Tile64 Overfetch via MMIO

Signed-off-by: default avatarApoorva Singh <apoorva.singh@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241107082158.1436637-1-apoorva.singh@intel.com


Signed-off-by: default avatarHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent f161809b

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -445,6 +445,8 @@ 


#define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)

#define   ENABLE_SMALLPL			REG_BIT(15)

#define   SMP_WAIT_FETCH_MERGING_COUNTER	REG_GENMASK(11, 10)

#define   SMP_FORCE_128B_OVERFETCH		REG_FIELD_PREP(SMP_WAIT_FETCH_MERGING_COUNTER, 1)

#define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)

#define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)

#define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)

drivers/gpu/drm/xe/xe_wa.c

+6 −0
Original line number Diff line number Diff line
@@ -607,6 +607,12 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
		       FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))

	},

	{ XE_RTP_NAME("16024792527"),

	  XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),

		       FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,

				   SMP_FORCE_128B_OVERFETCH))

	},



	{}

};