Commit f8d355bf authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v6.13-tag1' of... 

Merge tag 'renesas-pinctrl-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers

 into devel

pinctrl: renesas: Updates for v6.13

  - Marks GPIOs as used on RZ/A1 and RZ/A2,
  - Add open-drain and schmitt-trigger support on RZ/V2H(P),
  - Miscellaneous fixes and improvements.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents a83c29e1 5dcde519

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+4 −0
Original line number Diff line number Diff line
@@ -119,6 +119,10 @@ additionalProperties: 
        bias-disable: true

        bias-pull-down: true

        bias-pull-up: true

        input-schmitt-enable: true

        input-schmitt-disable: true

        drive-open-drain: true

        drive-push-pull: true

        renesas,output-impedance:

          description:

            Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this

drivers/pinctrl/renesas/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ config PINCTRL_RENESAS 
	select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0

	select PINCTRL_RZG2L if ARCH_RZG2L

	select PINCTRL_RZV2M if ARCH_R9A09G011

	select PINCTRL_RZG2L if ARCH_R9A09G057

	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203

	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269

drivers/pinctrl/renesas/pinctrl-rza1.c

+7 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <linux/ioport.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/pinctrl/consumer.h>

#include <linux/pinctrl/pinconf-generic.h>

#include <linux/pinctrl/pinctrl.h>

#include <linux/pinctrl/pinmux.h>
@@ -750,6 +751,11 @@ static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, 
static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)

{

	struct rza1_port *port = gpiochip_get_data(chip);

	int ret;



	ret = pinctrl_gpio_request(chip, gpio);

	if (ret)

		return ret;



	rza1_pin_reset(port, gpio);
@@ -771,6 +777,7 @@ static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio) 
	struct rza1_port *port = gpiochip_get_data(chip);



	rza1_pin_reset(port, gpio);

	pinctrl_gpio_free(chip, gpio);

}



static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)

drivers/pinctrl/renesas/pinctrl-rza2.c

+3 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <linux/module.h>

#include <linux/mutex.h>

#include <linux/of.h>

#include <linux/pinctrl/consumer.h>

#include <linux/pinctrl/pinmux.h>

#include <linux/platform_device.h>
@@ -229,6 +230,8 @@ static const char * const rza2_gpio_names[] = { 
static struct gpio_chip chip = {

	.names = rza2_gpio_names,

	.base = -1,

	.request = pinctrl_gpio_request,

	.free = pinctrl_gpio_free,

	.get_direction = rza2_chip_get_direction,

	.direction_input = rza2_chip_direction_input,

	.direction_output = rza2_chip_direction_output,

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+48 −3
Original line number Diff line number Diff line
@@ -139,6 +139,8 @@ 
#define IEN(off)		(0x1800 + (off) * 8)

#define PUPD(off)		(0x1C00 + (off) * 8)

#define ISEL(off)		(0x2C00 + (off) * 8)

#define NOD(off)		(0x3000 + (off) * 8)

#define SMT(off)		(0x3400 + (off) * 8)

#define SD_CH(off, ch)		((off) + (ch) * 4)

#define ETH_POC(off, ch)	((off) + (ch) * 4)

#define QSPI			(0x3008)
@@ -160,6 +162,8 @@ 
#define IOLH_MASK		0x03

#define SR_MASK			0x01

#define PUPD_MASK		0x03

#define NOD_MASK		0x01

#define SMT_MASK		0x01



#define PM_INPUT		0x1

#define PM_OUTPUT		0x2
@@ -168,7 +172,6 @@ 
#define RZG2L_PIN_ID_TO_PIN(id)		((id) % RZG2L_PINS_PER_PORT)



#define RZG2L_TINT_MAX_INTERRUPT	32

#define RZG2L_TINT_IRQ_START_INDEX	9

#define RZG2L_PACK_HWIRQ(t, i)		(((t) << 16) | (i))



/* Custom pinconf parameters */
@@ -247,6 +250,7 @@ enum rzg2l_iolh_index { 
 * @iolh_groupb_ua: IOLH group B uA specific values

 * @iolh_groupc_ua: IOLH group C uA specific values

 * @iolh_groupb_oi: IOLH group B output impedance specific values

 * @tint_start_index: the start index for the TINT interrupts

 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)

 * @func_base: base number for port function (see register PFC)

 * @oen_max_pin: the maximum pin number supporting output enable
@@ -258,6 +262,7 @@ struct rzg2l_hwcfg { 
	u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];

	u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];

	u16 iolh_groupb_oi[4];

	u16 tint_start_index;

	bool drive_strength_ua;

	u8 func_base;

	u8 oen_max_pin;
@@ -1337,6 +1342,27 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 
		break;

	}



	case PIN_CONFIG_DRIVE_OPEN_DRAIN:

	case PIN_CONFIG_DRIVE_PUSH_PULL:

		if (!(cfg & PIN_CFG_NOD))

			return -EINVAL;



		arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK);

		if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL)

			return -EINVAL;

		if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN)

			return -EINVAL;

		break;



	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:

		if (!(cfg & PIN_CFG_SMT))

			return -EINVAL;



		arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK);

		if (!arg)

			return -EINVAL;

		break;



	case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:

		if (!(cfg & PIN_CFG_IOLH_RZV2H))

			return -EINVAL;
@@ -1466,6 +1492,22 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
			rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);

			break;



		case PIN_CONFIG_DRIVE_OPEN_DRAIN:

		case PIN_CONFIG_DRIVE_PUSH_PULL:

			if (!(cfg & PIN_CFG_NOD))

				return -EINVAL;



			rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK,

					     param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0);

			break;



		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:

			if (!(cfg & PIN_CFG_SMT))

				return -EINVAL;



			rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg);

			break;



		case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:

			if (!(cfg & PIN_CFG_IOLH_RZV2H))

				return -EINVAL;
@@ -2379,7 +2421,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 


	rzg2l_gpio_irq_endisable(pctrl, child, true);

	pctrl->hwirq[irq] = child;

	irq += RZG2L_TINT_IRQ_START_INDEX;

	irq += pctrl->data->hwcfg->tint_start_index;



	/* All these interrupts are level high in the CPU */

	*parent_type = IRQ_TYPE_LEVEL_HIGH;
@@ -2710,7 +2752,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 


	ret = pinctrl_enable(pctrl->pctl);

	if (ret)

		dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");

		return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");



	ret = rzg2l_gpio_register(pctrl);

	if (ret)
@@ -3034,6 +3076,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { 
		[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,

	},

	.iolh_groupb_oi = { 100, 66, 50, 33, },

	.tint_start_index = 9,

	.oen_max_pin = 0,

};
@@ -3063,6 +3106,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { 
		/* 3v3 power source */

		[RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,

	},

	.tint_start_index = 9,

	.drive_strength_ua = true,

	.func_base = 1,

	.oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
@@ -3073,6 +3117,7 @@ static const struct rzg2l_hwcfg rzv2h_hwcfg = { 
	.regs = {

		.pwpr = 0x3c04,

	},

	.tint_start_index = 17,

};



static struct rzg2l_pinctrl_data r9a07g043_data = {