Commit f91a3a60 authored by Kevin Brodsky's avatar Kevin Brodsky Committed by Catalin Marinas
Browse files

arm64/sysreg: Improve PIR/POR helpers 



We currently have one helper to set a PIRx_ELx's permission field to
a given value, PIRx_ELx_PERM(), and another helper to extract a
permission field from POR_ELx, POR_ELx_IDX(). The naming is pretty
confusing - it isn't clear at all that "_PERM" corresponds to a
setter and "_IDX" to a getter.

This patch aims at improving the situation by using the same
suffixes as FIELD_PREP()/FIELD_GET(), which we have already adopted
for SYS_FIELD_{PREP,GET}():

* PIRx_ELx_PERM_PREP(), POR_ELx_PERM_PREP() create a register value
  where the permission field for a given index is set to a given value.

* POR_ELx_PERM_GET() extracts the permission field from a given
  register value for a given index.

These helpers are not implemented using FIELD_PREP()/FIELD_GET()
because the mask may not be constant, and they need to be usable in
assembly. They are all defined in asm/sysreg.h, as one would expect
for basic sysreg-related helpers.

Finally the new POR_ELx_PERM_* macros are used for existing
calculations in signal.c and mmu.c.

Signed-off-by: default avatarKevin Brodsky <kevin.brodsky@arm.com>
Link: https://lore.kernel.org/r/20250219164029.2309119-2-kevin.brodsky@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 0ad2507d

arch/arm64/include/asm/pgtable-prot.h

+18 −18
Original line number Diff line number Diff line
@@ -169,25 +169,25 @@ static inline bool __pure lpa2_is_enabled(void) 
#define PAGE_GCS_RO	__pgprot(_PAGE_GCS_RO)



#define PIE_E0	( \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS),           PIE_GCS)  | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS_RO),        PIE_R)   | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O)  | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX_O) | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R_O)   | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW_O))

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS),           PIE_GCS)  | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO),        PIE_R)   | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O)  | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX_O) | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY),      PIE_R_O)   | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED),        PIE_RW_O))



#define PIE_E1	( \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS),           PIE_NONE_O) | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_GCS_RO),        PIE_NONE_O) | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \

	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL),        PIE_RW))

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS),           PIE_NONE_O) | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO),        PIE_NONE_O) | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \

	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL),        PIE_RW))



#endif /* __ASM_PGTABLE_PROT_H */

arch/arm64/include/asm/por.h

+4 −5
Original line number Diff line number Diff line
@@ -6,26 +6,25 @@ 
#ifndef _ASM_ARM64_POR_H

#define _ASM_ARM64_POR_H



#define POR_BITS_PER_PKEY		4

#define POR_ELx_IDX(por_elx, idx)	(((por_elx) >> ((idx) * POR_BITS_PER_PKEY)) & 0xf)

#include <asm/sysreg.h>



static inline bool por_elx_allows_read(u64 por, u8 pkey)

{

	u8 perm = POR_ELx_IDX(por, pkey);

	u8 perm = POR_ELx_PERM_GET(pkey, por);



	return perm & POE_R;

}



static inline bool por_elx_allows_write(u64 por, u8 pkey)

{

	u8 perm = POR_ELx_IDX(por, pkey);

	u8 perm = POR_ELx_PERM_GET(pkey, por);



	return perm & POE_W;

}



static inline bool por_elx_allows_exec(u64 por, u8 pkey)

{

	u8 perm = POR_ELx_IDX(por, pkey);

	u8 perm = POR_ELx_PERM_GET(pkey, por);



	return perm & POE_X;

}

arch/arm64/include/asm/sysreg.h

+9 −1
Original line number Diff line number Diff line
@@ -1062,8 +1062,11 @@ 
#define PIE_RX		UL(0xa)

#define PIE_RW		UL(0xc)

#define PIE_RWX		UL(0xe)

#define PIE_MASK	UL(0xf)



#define PIRx_ELx_PERM(idx, perm)	((perm) << ((idx) * 4))

#define PIRx_ELx_BITS_PER_IDX		4

#define PIRx_ELx_PERM_SHIFT(idx)	((idx) * PIRx_ELx_BITS_PER_IDX)

#define PIRx_ELx_PERM_PREP(idx, perm)	(((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx))



/*

 * Permission Overlay Extension (POE) permission encodings.
@@ -1078,6 +1081,11 @@ 
#define POE_RXW		UL(0x7)

#define POE_MASK	UL(0xf)



#define POR_ELx_BITS_PER_IDX		4

#define POR_ELx_PERM_SHIFT(idx)		((idx) * POR_ELx_BITS_PER_IDX)

#define POR_ELx_PERM_GET(idx, reg)	(((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK)

#define POR_ELx_PERM_PREP(idx, perm)	(((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx))



/* Initial value for Permission Overlay Extension for EL0 */

#define POR_EL0_INIT	POE_RXW

arch/arm64/kernel/signal.c

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static void save_reset_user_access_state(struct user_access_state *ua_state) 
		u64 por_enable_all = 0;



		for (int pkey = 0; pkey < arch_max_pkey(); pkey++)

			por_enable_all |= POE_RXW << (pkey * POR_BITS_PER_PKEY);

			por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RXW);



		ua_state->por_el0 = read_sysreg_s(SYS_POR_EL0);

		write_sysreg_s(por_enable_all, SYS_POR_EL0);

arch/arm64/mm/mmu.c

+2 −4
Original line number Diff line number Diff line
@@ -1557,7 +1557,6 @@ int arch_set_user_pkey_access(struct task_struct *tsk, int pkey, unsigned long i 
{

	u64 new_por = POE_RXW;

	u64 old_por;

	u64 pkey_shift;



	if (!system_supports_poe())

		return -ENOSPC;
@@ -1582,12 +1581,11 @@ int arch_set_user_pkey_access(struct task_struct *tsk, int pkey, unsigned long i 
		new_por &= ~POE_X;



	/* Shift the bits in to the correct place in POR for pkey: */

	pkey_shift = pkey * POR_BITS_PER_PKEY;

	new_por <<= pkey_shift;

	new_por = POR_ELx_PERM_PREP(pkey, new_por);



	/* Get old POR and mask off any old bits in place: */

	old_por = read_sysreg_s(SYS_POR_EL0);

	old_por &= ~(POE_MASK << pkey_shift);

	old_por &= ~(POE_MASK << POR_ELx_PERM_SHIFT(pkey));



	/* Write old part along with new part: */

	write_sysreg_s(old_por | new_por, SYS_POR_EL0);