Commit f91bacce authored by Matt Roper's avatar Matt Roper Committed by Rodrigo Vivi
Browse files

drm/xe/dg2: Drop Wa_22014600077 



The workaround database has been updated to drop this workaround for all
DG2 variants.

Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231127190332.4099519-2-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 812ec747

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+0 −1
Original line number Diff line number Diff line
@@ -340,7 +340,6 @@ 
#define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)



#define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)

#define   ENABLE_EU_COUNT_FOR_TDL_FLUSH		REG_BIT(10)

#define   DISABLE_ECC				REG_BIT(5)

#define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)

drivers/gpu/drm/xe/xe_wa.c

+0 −21
Original line number Diff line number Diff line
@@ -522,27 +522,6 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,

			     DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))

	},

	{ XE_RTP_NAME("22014600077"),

	  XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(B0, FOREVER),

		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS,

			     ENABLE_EU_COUNT_FOR_TDL_FLUSH,

			     /*

			      * Wa_14012342262 write-only reg, so skip

			      * verification

			      */

			     .read_mask = 0))

	},

	{ XE_RTP_NAME("22014600077"),

	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS,

			     ENABLE_EU_COUNT_FOR_TDL_FLUSH,

			     /*

			      * Wa_14012342262 write-only reg, so skip

			      * verification

			      */

			     .read_mask = 0))

	},

	{ XE_RTP_NAME("14015150844"),

	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,