Commit f91c69f4 authored by Carolina Jubran's avatar Carolina Jubran Committed by Paolo Abeni
Browse files

net/mlx5: Unify QoS element type checks across NIC and E-Switch 



Refactor the QoS element type support check by introducing a new
function, mlx5_qos_element_type_supported(), which handles element type
validation for both NIC and E-Switch schedulers.

This change removes the redundant esw_qos_element_type_supported()
function and unifies the element type checks into a single
implementation.

Signed-off-by: default avatarCarolina Jubran <cjubran@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 40efb0b7

drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c

+6 −21
Original line number Diff line number Diff line
@@ -371,25 +371,6 @@ static int esw_qos_set_group_max_rate(struct mlx5_esw_rate_group *group, 
	return err;

}



static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)

{

	switch (type) {

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:

		return MLX5_CAP_QOS(dev, esw_element_type) &

		       ELEMENT_TYPE_CAP_MASK_TSAR;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:

		return MLX5_CAP_QOS(dev, esw_element_type) &

		       ELEMENT_TYPE_CAP_MASK_VPORT;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:

		return MLX5_CAP_QOS(dev, esw_element_type) &

		       ELEMENT_TYPE_CAP_MASK_VPORT_TC;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:

		return MLX5_CAP_QOS(dev, esw_element_type) &

		       ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;

	}

	return false;

}



static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport,

					      u32 max_rate, u32 bw_share)

{
@@ -399,7 +380,9 @@ static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, 
	void *attr;

	int err;



	if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT))

	if (!mlx5_qos_element_type_supported(dev,

					     SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT,

					     SCHEDULING_HIERARCHY_E_SWITCH))

		return -EOPNOTSUPP;



	MLX5_SET(scheduling_context, sched_ctx, element_type,
@@ -616,7 +599,9 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta 
	if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))

		return -EOPNOTSUPP;



	if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR) ||

	if (!mlx5_qos_element_type_supported(dev,

					     SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR,

					     SCHEDULING_HIERARCHY_E_SWITCH) ||

	    !(MLX5_CAP_QOS(dev, esw_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))

		return -EOPNOTSUPP;

drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h

+1 −0
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ void mlx5_sriov_disable(struct pci_dev *pdev, bool num_vf_change); 
int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count);

int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);

int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);

bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy);

int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,

				       void *context, u32 *element_id);

int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,

drivers/net/ethernet/mellanox/mlx5/core/qos.c

+6 −2
Original line number Diff line number Diff line
@@ -28,7 +28,9 @@ int mlx5_qos_create_leaf_node(struct mlx5_core_dev *mdev, u32 parent_id, 
{

	u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};



	if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP))

	if (!mlx5_qos_element_type_supported(mdev,

					     SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP,

					     SCHEDULING_HIERARCHY_NIC))

		return -EOPNOTSUPP;



	MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
@@ -47,7 +49,9 @@ int mlx5_qos_create_inner_node(struct mlx5_core_dev *mdev, u32 parent_id, 
	u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};

	void *attr;



	if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_TSAR) ||

	if (!mlx5_qos_element_type_supported(mdev,

					     SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR,

					     SCHEDULING_HIERARCHY_NIC) ||

	    !(MLX5_CAP_QOS(mdev, nic_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))

		return -EOPNOTSUPP;

drivers/net/ethernet/mellanox/mlx5/core/rl.c

+31 −0
Original line number Diff line number Diff line
@@ -34,6 +34,37 @@ 
#include <linux/mlx5/driver.h>

#include "mlx5_core.h"



bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy)

{

	int cap;



	switch (hierarchy) {

	case SCHEDULING_HIERARCHY_E_SWITCH:

		cap = MLX5_CAP_QOS(dev, esw_element_type);

		break;

	case SCHEDULING_HIERARCHY_NIC:

		cap = MLX5_CAP_QOS(dev, nic_element_type);

		break;

	default:

		return false;

	}



	switch (type) {

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:

		return cap & ELEMENT_TYPE_CAP_MASK_TSAR;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:

		return cap & ELEMENT_TYPE_CAP_MASK_VPORT;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:

		return cap & ELEMENT_TYPE_CAP_MASK_VPORT_TC;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:

		return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP:

		return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP;

	}



	return false;

}



/* Scheduling element fw management */

int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,

				       void *ctx, u32 *element_id)