Commit f96012ba authored by Ilya Bakoulin's avatar Ilya Bakoulin Committed by Alex Deucher
Browse files

drm/amd/display: add new block sequence-building/executing functions 



[Why/How]
Create functions for building/executing HW block programming steps

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarIlya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c6a0234

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

+2973 −188

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -1165,6 +1165,7 @@ struct dc_debug_options { 
	unsigned int auxless_alpm_lfps_t1t2_us;

	short auxless_alpm_lfps_t1t2_offset_us;

	bool disable_stutter_for_wm_program;

	bool enable_block_sequence_programming;

};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

+1345 −7

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

+98 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include "dc.h"

#include "dc_stream.h"

#include "hw_sequencer_private.h"

#include "hwss/hw_sequencer.h"

#include "dcn401/dcn401_dccg.h"



struct dc;
@@ -82,6 +83,8 @@ void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *l 
void dcn401_hardware_release(struct dc *dc);

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

		struct pipe_ctx *otg_master);

void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,

		struct pipe_ctx *otg_master, struct block_sequence_state *seq_state);

void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy);

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);
@@ -97,6 +100,11 @@ void dcn401_program_pipe( 
	struct dc *dc,

	struct pipe_ctx *pipe_ctx,

	struct dc_state *context);

void dcn401_program_pipe_sequence(

	struct dc *dc,

	struct pipe_ctx *pipe_ctx,

	struct dc_state *context,

	struct block_sequence_state *seq_state);

void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx);

void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context);

void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context);
@@ -109,7 +117,97 @@ void dcn401_detect_pipe_changes( 
void dcn401_plane_atomic_power_down(struct dc *dc,

		struct dpp *dpp,

		struct hubp *hubp);

void dcn401_plane_atomic_power_down_sequence(struct dc *dc,

		struct dpp *dpp,

		struct hubp *hubp,

		struct block_sequence_state *seq_state);

void dcn401_plane_atomic_disconnect_sequence(struct dc *dc,

		struct dc_state *state,

		struct pipe_ctx *pipe_ctx,

		struct block_sequence_state *seq_state);

void dcn401_blank_pixel_data_sequence(

	struct dc *dc,

	struct pipe_ctx *pipe_ctx,

	bool blank,

	struct block_sequence_state *seq_state);

void dcn401_initialize_min_clocks(struct dc *dc);

void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);



void dcn401_program_all_writeback_pipes_in_tree_sequence(

		struct dc *dc,

		const struct dc_stream_state *stream,

		struct dc_state *context,

		struct block_sequence_state *seq_state);



void dcn401_enable_writeback_sequence(

		struct dc *dc,

		struct dc_writeback_info *wb_info,

		struct dc_state *context,

		int mpcc_inst,

		struct block_sequence_state *seq_state);



void dcn401_disable_writeback_sequence(

		struct dc *dc,

		struct dc_writeback_info *wb_info,

		struct block_sequence_state *seq_state);



void dcn401_update_writeback_sequence(

		struct dc *dc,

		struct dc_writeback_info *wb_info,

		struct dc_state *context,

		struct block_sequence_state *seq_state);



void dcn401_setup_gsl_group_as_lock_sequence(

		const struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		bool enable,

		struct block_sequence_state *seq_state);



void dcn401_disable_plane_sequence(

		struct dc *dc,

		struct dc_state *state,

		struct pipe_ctx *pipe_ctx,

		struct block_sequence_state *seq_state);



void dcn401_post_unlock_reset_opp_sequence(

		struct dc *dc,

		struct pipe_ctx *opp_head,

		struct block_sequence_state *seq_state);



void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable);



void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

				 struct dc_state *context,

				 struct block_sequence_state *seq_state);



void dcn401_update_dchubp_dpp_sequence(struct dc *dc,

				       struct pipe_ctx *pipe_ctx,

				       struct dc_state *context,

				       struct block_sequence_state *seq_state);



void dcn401_update_mpcc_sequence(struct dc *dc,

				struct pipe_ctx *pipe_ctx,

				struct block_sequence_state *seq_state);



void dcn401_wait_for_mpcc_disconnect_sequence(

		struct dc *dc,

		struct resource_pool *res_pool,

		struct pipe_ctx *pipe_ctx,

		struct block_sequence_state *seq_state);



void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

		struct block_sequence_state *seq_state);



void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,

		struct block_sequence_state *seq_state);



void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,

		struct block_sequence_state *seq_state);



void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc,

		struct block_sequence_state *seq_state);



bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc,

		struct block_sequence_state *seq_state);



#endif /* __DC_HWSS_DCN401_H__ */

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

+17 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { 
	.enable_audio_stream = dce110_enable_audio_stream,

	.disable_audio_stream = dce110_disable_audio_stream,

	.disable_plane = dcn20_disable_plane,

	.disable_plane_sequence = dcn401_disable_plane_sequence,

	.pipe_control_lock = dcn20_pipe_control_lock,

	.interdependent_update_lock = dcn401_interdependent_update_lock,

	.cursor_lock = dcn10_cursor_lock,
@@ -54,6 +55,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { 
	.get_hw_state = dcn10_get_hw_state,

	.clear_status_bits = dcn10_clear_status_bits,

	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,

	.wait_for_mpcc_disconnect_sequence = dcn401_wait_for_mpcc_disconnect_sequence,

	.edp_backlight_control = dce110_edp_backlight_control,

	.edp_power_control = dce110_edp_power_control,

	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
@@ -109,48 +111,63 @@ static const struct hw_sequencer_funcs dcn401_funcs = { 
	.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,

	.detect_pipe_changes = dcn401_detect_pipe_changes,

	.enable_plane = dcn20_enable_plane,

	.enable_plane_sequence = dcn401_enable_plane_sequence,

	.update_dchubp_dpp = dcn20_update_dchubp_dpp,

	.update_dchubp_dpp_sequence = dcn401_update_dchubp_dpp_sequence,

	.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,

	.post_unlock_reset_opp_sequence = dcn401_post_unlock_reset_opp_sequence,

	.get_underflow_debug_data = dcn30_get_underflow_debug_data,

};



static const struct hwseq_private_funcs dcn401_private_funcs = {

	.init_pipes = dcn10_init_pipes,

	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,

	.plane_atomic_disconnect_sequence = dcn401_plane_atomic_disconnect_sequence,

	.update_mpcc = dcn20_update_mpcc,

	.update_mpcc_sequence = dcn401_update_mpcc_sequence,

	.set_input_transfer_func = dcn32_set_input_transfer_func,

	.set_output_transfer_func = dcn401_set_output_transfer_func,

	.power_down = dce110_power_down,

	.enable_display_power_gating = dcn10_dummy_display_power_gating,

	.blank_pixel_data = dcn20_blank_pixel_data,

	.blank_pixel_data_sequence = dcn401_blank_pixel_data_sequence,

	.reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap,

	.enable_stream_timing = dcn401_enable_stream_timing,

	.edp_backlight_control = dce110_edp_backlight_control,

	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,

	.setup_vupdate_interrupt_sequence = dcn401_setup_vupdate_interrupt_sequence,

	.did_underflow_occur = dcn10_did_underflow_occur,

	.init_blank = dcn32_init_blank,

	.disable_vga = dcn20_disable_vga,

	.bios_golden_init = dcn10_bios_golden_init,

	.plane_atomic_disable = dcn20_plane_atomic_disable,

	.plane_atomic_power_down = dcn401_plane_atomic_power_down,

	.plane_atomic_power_down_sequence = dcn401_plane_atomic_power_down_sequence,

	.enable_power_gating_plane = dcn32_enable_power_gating_plane,

	.hubp_pg_control = dcn32_hubp_pg_control,

	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,

	.program_all_writeback_pipes_in_tree_sequence = dcn401_program_all_writeback_pipes_in_tree_sequence,

	.update_odm = dcn401_update_odm,

	.update_odm_sequence = dcn401_update_odm_sequence,

	.dsc_pg_control = dcn32_dsc_pg_control,

	.dsc_pg_status = dcn32_dsc_pg_status,

	.set_hdr_multiplier = dcn10_set_hdr_multiplier,

	.set_hdr_multiplier_sequence = dcn401_set_hdr_multiplier_sequence,

	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,

	.verify_allow_pstate_change_high_sequence = dcn401_verify_allow_pstate_change_high_sequence,

	.wait_for_blank_complete = dcn20_wait_for_blank_complete,

	.dccg_init = dcn20_dccg_init,

	.set_mcm_luts = dcn401_set_mcm_luts,

	.program_mall_pipe_config = dcn32_program_mall_pipe_config,

	.program_mall_pipe_config_sequence = dcn401_program_mall_pipe_config_sequence,

	.update_mall_sel = dcn32_update_mall_sel,

	.calculate_dccg_k1_k2_values = NULL,

	.apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,

	.reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe,

	.populate_mcm_luts = NULL,

	.perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock,

	.program_pipe_sequence = dcn401_program_pipe_sequence,

	.dc_ip_request_cntl = dcn401_dc_ip_request_cntl,

};



void dcn401_hw_sequencer_init_functions(struct dc *dc)