Commit f9af88a3 authored by Borislav Petkov (AMD)'s avatar Borislav Petkov (AMD)
Browse files

x86/bugs: Rename MDS machinery to something more generic 



It will be used by other x86 mitigations.

No functional changes.

Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarPawan Gupta <pawan.kumar.gupta@linux.intel.com>
parent e04c78d8

Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst

+1 −3
Original line number Diff line number Diff line
@@ -157,9 +157,7 @@ This is achieved by using the otherwise unused and obsolete VERW instruction in 
combination with a microcode update. The microcode clears the affected CPU

buffers when the VERW instruction is executed.



Kernel reuses the MDS function to invoke the buffer clearing:



	mds_clear_cpu_buffers()

Kernel does the buffer clearing with x86_clear_cpu_buffers().



On MDS affected CPUs, the kernel already invokes CPU buffer clear on

kernel/userspace, hypervisor/guest and C-state (idle) transitions. No

Documentation/arch/x86/mds.rst

+4 −4
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ enters a C-state. 


The kernel provides a function to invoke the buffer clearing:



    mds_clear_cpu_buffers()

    x86_clear_cpu_buffers()



Also macro CLEAR_CPU_BUFFERS can be used in ASM late in exit-to-user path.

Other than CFLAGS.ZF, this macro doesn't clobber any registers.
@@ -185,9 +185,9 @@ Mitigation points 
   idle clearing would be a window dressing exercise and is therefore not

   activated.



   The invocation is controlled by the static key mds_idle_clear which is

   switched depending on the chosen mitigation mode and the SMT state of

   the system.

   The invocation is controlled by the static key cpu_buf_idle_clear which is

   switched depending on the chosen mitigation mode and the SMT state of the

   system.



   The buffer clear is only invoked before entering the C-State to prevent

   that stale data from the idling CPU from spilling to the Hyper-Thread

arch/x86/entry/entry.S

+4 −4
Original line number Diff line number Diff line
@@ -36,20 +36,20 @@ EXPORT_SYMBOL_GPL(write_ibpb); 


/*

 * Define the VERW operand that is disguised as entry code so that

 * it can be referenced with KPTI enabled. This ensure VERW can be

 * it can be referenced with KPTI enabled. This ensures VERW can be

 * used late in exit-to-user path after page tables are switched.

 */

.pushsection .entry.text, "ax"



.align L1_CACHE_BYTES, 0xcc

SYM_CODE_START_NOALIGN(mds_verw_sel)

SYM_CODE_START_NOALIGN(x86_verw_sel)

	UNWIND_HINT_UNDEFINED

	ANNOTATE_NOENDBR

	.word __KERNEL_DS

.align L1_CACHE_BYTES, 0xcc

SYM_CODE_END(mds_verw_sel);

SYM_CODE_END(x86_verw_sel);

/* For KVM */

EXPORT_SYMBOL_GPL(mds_verw_sel);

EXPORT_SYMBOL_GPL(x86_verw_sel);



.popsection

arch/x86/include/asm/irqflags.h

+2 −2
Original line number Diff line number Diff line
@@ -44,13 +44,13 @@ static __always_inline void native_irq_enable(void) 


static __always_inline void native_safe_halt(void)

{

	mds_idle_clear_cpu_buffers();

	x86_idle_clear_cpu_buffers();

	asm volatile("sti; hlt": : :"memory");

}



static __always_inline void native_halt(void)

{

	mds_idle_clear_cpu_buffers();

	x86_idle_clear_cpu_buffers();

	asm volatile("hlt": : :"memory");

}

arch/x86/include/asm/mwait.h

+2 −2
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx) 


static __always_inline void __mwait(u32 eax, u32 ecx)

{

	mds_idle_clear_cpu_buffers();

	x86_idle_clear_cpu_buffers();



	/*

	 * Use the instruction mnemonic with implicit operands, as the LLVM
@@ -98,7 +98,7 @@ static __always_inline void __mwaitx(u32 eax, u32 ebx, u32 ecx) 
 */

static __always_inline void __sti_mwait(u32 eax, u32 ecx)

{

	mds_idle_clear_cpu_buffers();

	x86_idle_clear_cpu_buffers();



	asm volatile("sti; mwait" :: "a" (eax), "c" (ecx));

}