Commit f9b11aa0 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Will Deacon
Browse files

KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access



ARMV8_PMU_COUNTER_MASK is really a mask for the PMSELR_EL0.SEL register
field. Make that clear by adding a standard sysreg definition for the
register, and using it instead.

Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Tested-by: default avatarJames Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-4-280a8d7ff465@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 741ee528
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+0 −1
Original line number Diff line number Diff line
@@ -403,7 +403,6 @@
#define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
#define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
#define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
#define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
#define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
#define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
#define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
+5 −5
Original line number Diff line number Diff line
@@ -887,7 +887,7 @@ static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
	reset_unknown(vcpu, r);
	__vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
	__vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;

	return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -979,7 +979,7 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
	else
		/* return PMSELR.SEL field */
		p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
			    & ARMV8_PMU_COUNTER_MASK;
			    & PMSELR_EL0_SEL_MASK;

	return true;
}
@@ -1047,8 +1047,8 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
			if (pmu_access_event_counter_el0_disabled(vcpu))
				return false;

			idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
			      & ARMV8_PMU_COUNTER_MASK;
			idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
					    __vcpu_sys_reg(vcpu, PMSELR_EL0));
		} else if (r->Op2 == 0) {
			/* PMCCNTR_EL0 */
			if (pmu_access_cycle_counter_el0_disabled(vcpu))
@@ -1098,7 +1098,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,

	if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
		/* PMXEVTYPER_EL0 */
		idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
		idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
		reg = PMEVTYPER0_EL0 + idx;
	} else if (r->CRn == 14 && (r->CRm & 12) == 12) {
		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
+5 −0
Original line number Diff line number Diff line
@@ -2153,6 +2153,11 @@ Field 4 P
Field	3:0	ALIGN
EndSysreg

Sysreg	PMSELR_EL0	3	3	9	12	5
Res0	63:5
Field	4:0	SEL
EndSysreg

SysregFields	CONTEXTIDR_ELx
Res0	63:32
Field	31:0	PROCID
+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@

#define ARMV8_PMU_MAX_GENERAL_COUNTERS	31
#define ARMV8_PMU_MAX_COUNTERS	32
#define ARMV8_PMU_COUNTER_MASK	(ARMV8_PMU_MAX_COUNTERS - 1)

/*
 * Common architectural and microarchitectural event numbers.