Commit f9ce482d authored by Jonathan Marek's avatar Jonathan Marek Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: fix video mode DSC for DSI 



Add width change in DPU timing for DSC compression case to work with
DSI video mode.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/596227/
Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-1-2ab1d334c657@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 5372db09

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+1 −1
Original line number Diff line number Diff line
@@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 
	return (num_dsc > 0) && (num_dsc > intf_count);

}



static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)

struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)

{

	struct msm_drm_private *priv = drm_enc->dev->dev_private;

	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

+8 −0
Original line number Diff line number Diff line
@@ -339,6 +339,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( 
 */

unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);



/**

 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder

 *   This helper function is used by physical encoder to get DSC config

 *   used for this encoder.

 * @drm_enc: Pointer to encoder structure

 */

struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc);



/**

 * dpu_encoder_get_drm_fmt - return DRM fourcc format

 * @phys_enc: Pointer to physical encoder structure

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

+18 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include "dpu_trace.h"

#include "disp/msm_disp_snapshot.h"



#include <drm/display/drm_dsc_helper.h>

#include <drm/drm_managed.h>



#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
@@ -115,6 +116,23 @@ static void drm_mode_to_intf_timing_params( 
		timing->h_front_porch = timing->h_front_porch >> 1;

		timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;

	}



	/*

	 * for DSI, if compression is enabled, then divide the horizonal active

	 * timing parameters by compression ratio. bits of 3 components(R/G/B)

	 * is compressed into bits of 1 pixel.

	 */

	if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {

		struct drm_dsc_config *dsc =

		       dpu_encoder_get_dsc_config(phys_enc->parent);

		/*

		 * TODO: replace drm_dsc_get_bpp_int with logic to handle

		 * fractional part if there is fraction

		 */

		timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /

				(dsc->bits_per_component * 3);

		timing->xres = timing->width;

	}

}



static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)