Commit f9d41855 authored by Suraj Kandpal's avatar Suraj Kandpal
Browse files

drm/i915/cx0_phy: Fix C10 pll programming sequence 



According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
specific VDR registers and TX Lane programming registers are done.
Moreover we only program into C10_VDR_CONTROL1 to update config and
setup master lane once all VDR registers are written into.

Bspec: 67636
Fixes: 51390cc0 ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241216181554.2861381-1-suraj.kandpal@intel.com
parent 1e28fbf8

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+4 −8
Original line number Diff line number Diff line
@@ -2117,14 +2117,6 @@ static void intel_c10_pll_program(struct intel_display *display, 
		      0, C10_VDR_CTRL_MSGBUS_ACCESS,

		      MB_WRITE_COMMITTED);



	/* Custom width needs to be programmed to 0 for both the phy lanes */

	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,

		      C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,

		      MB_WRITE_COMMITTED);

	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),

		      0, C10_VDR_CTRL_UPDATE_CFG,

		      MB_WRITE_COMMITTED);



	/* Program the pll values only for the master lane */

	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)

		intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),
@@ -2134,6 +2126,10 @@ static void intel_c10_pll_program(struct intel_display *display, 
	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);

	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);



	/* Custom width needs to be programmed to 0 for both the phy lanes */

	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,

		      C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,

		      MB_WRITE_COMMITTED);

	intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),

		      0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,

		      MB_WRITE_COMMITTED);