Commit fa5ef105 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "This release is almost entirely new drivers, with a couple of small
  changes in generic code.

  The biggest individual update is a rename of the existing Microchip
  driver and the addition of a new driver for the silicon SPI controller
  in their PolarFire SoCs. The overlap between the soft IP supported by
  the current driver and this new one is regrettably all in the IP and
  not in the register interface offered to software.

   - Add a time offset parameter for offloads, allowing them to be
     defined in relation to each other. This is useful for IIO type
     applcations where you trigger an operation then read the result
     after a delay.

   - Add a tracepoint for flash exec_ops, bringing the flash support
     more in line with the debuggability of vanilla SPI.

   - Support for Airoha EN7523, Arduino MCUs, Aspeed AST2700, Microchip
     PolarFire SPI controllers, NXP i.MX51 ECSPI target mode, Qualcomm
     IPQ5414 and IPQ5332, Renesas RZ/T2H, RZ/V2N and RZ/2NH and SpacemiT
     K1 QuadSPI.

  There's also a small set of ASoC cleanups that I mistakenly applied to
  the SPI tree and then put more stuff on top of before it was brought
  to my attention, sorry about that"

* tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (80 commits)
  spi: microchip-core: Refactor FIFO read and write handlers
  spi: ch341: fix out-of-bounds memory access in ch341_transfer_one
  spi: microchip-core: Remove unneeded PM related macro
  spi: microchip-core: Use SPI_MODE_X_MASK
  spi: microchip-core: Utilise temporary variable for struct device
  spi: microchip-core: Replace dead code (-ENOMEM error message)
  spi: microchip-core: use min() instead of min_t()
  spi: dt-bindings: airoha: add compatible for EN7523
  spi: airoha-snfi: en7523: workaround flash damaging if UART_TXD was short to GND
  spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
  spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
  spi: microchip: Enable compile-testing for FPGA SPI controllers
  spi: Fix potential uninitialized variable in probe()
  spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H
  spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H
  spi: rzv2h-rspi: add support for loopback mode
  spi: rzv2h-rspi: add support for variable transfer clock
  spi: rzv2h-rspi: add support for using PCLK for transfer clock
  spi: rzv2h-rspi: make transfer clock rate finding chip-specific
  spi: rzv2h-rspi: avoid recomputing transfer frequency
  ...
parents 0a9431fa cb5c2eb4

Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml

+6 −1
Original line number Diff line number Diff line
@@ -14,7 +14,12 @@ allOf: 


properties:

  compatible:

    const: airoha,en7581-snand

    oneOf:

      - const: airoha,en7581-snand

      - items:

          - enum:

              - airoha,en7523-snand

          - const: airoha,en7581-snand



  reg:

    items:

Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml

+3 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ maintainers: 


description: |

  This binding describes the Aspeed Static Memory Controllers (FMC and

  SPI) of the AST2400, AST2500 and AST2600 SOCs.

  SPI) of the AST2400, AST2500, AST2600 and AST2700 SOCs.



allOf:

  - $ref: spi-controller.yaml#
@@ -20,6 +20,8 @@ allOf: 
properties:

  compatible:

    enum:

      - aspeed,ast2700-fmc

      - aspeed,ast2700-spi

      - aspeed,ast2600-fmc

      - aspeed,ast2600-spi

      - aspeed,ast2500-fmc

Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml

+18 −3
Original line number Diff line number Diff line
@@ -9,9 +9,6 @@ title: Freescale Quad Serial Peripheral Interface (QuadSPI) 
maintainers:

  - Han Xu <han.xu@nxp.com>



allOf:

  - $ref: spi-controller.yaml#



properties:

  compatible:

    oneOf:
@@ -22,6 +19,7 @@ properties: 
          - fsl,imx6ul-qspi

          - fsl,ls1021a-qspi

          - fsl,ls2080a-qspi

          - spacemit,k1-qspi

      - items:

          - enum:

              - fsl,ls1043a-qspi
@@ -54,6 +52,11 @@ properties: 
      - const: qspi_en

      - const: qspi



  resets:

    items:

      - description: SoC QSPI reset

      - description: SoC QSPI bus reset



required:

  - compatible

  - reg
@@ -62,6 +65,18 @@ required: 
  - clocks

  - clock-names



allOf:

  - $ref: spi-controller.yaml#

  - if:

      properties:

        compatible:

          not:

            contains:

              const: spacemit,k1-qspi

    then:

      properties:

        resets: false



unevaluatedProperties: false



examples:

Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml

+68 −2
Original line number Diff line number Diff line
@@ -21,11 +21,13 @@ properties: 
              - microchip,mpfs-qspi

              - microchip,pic64gx-qspi

          - const: microchip,coreqspi-rtl-v2

      - const: microchip,coreqspi-rtl-v2 # FPGA QSPI

      - enum:

          - microchip,coreqspi-rtl-v2 # FPGA QSPI

          - microchip,corespi-rtl-v5 # FPGA CoreSPI

          - microchip,mpfs-spi

      - items:

          - const: microchip,pic64gx-spi

          - const: microchip,mpfs-spi

      - const: microchip,mpfs-spi



  reg:

    maxItems: 1
@@ -39,6 +41,45 @@ properties: 
  clocks:

    maxItems: 1



  microchip,apb-datawidth:

    description: APB bus data width in bits.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [8, 16, 32]

    default: 8



  microchip,frame-size:

    description: |

      Number of bits per SPI frame, as configured in Libero.

      In Motorola and TI modes, this corresponds directly

      to the requested frame size. For NSC mode this is set

      to 9 + the required data frame size.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 4

    maximum: 32

    default: 8



  microchip,protocol-configuration:

    description: CoreSPI protocol selection. Determines operating mode

    $ref: /schemas/types.yaml#/definitions/string

    enum:

      - motorola

      - ti

      - nsc

    default: motorola



  microchip,motorola-mode:

    description: Motorola SPI mode selection

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2, 3]

    default: 3



  microchip,ssel-active:

    description: |

      Keep SSEL asserted between frames when using the Motorola protocol.

      When present, the controller keeps SSEL active across contiguous

      transfers and deasserts only when the overall transfer completes.

    type: boolean



required:

  - compatible

  - reg
@@ -71,6 +112,31 @@ allOf: 
        num-cs:

          maximum: 1



  - if:

      properties:

        compatible:

          contains:

            const: microchip,corespi-rtl-v5

    then:

      properties:

        num-cs:

          minimum: 1

          maximum: 8

          default: 8



        fifo-depth:

          minimum: 1

          maximum: 32

          default: 4



    else:

      properties:

        microchip,apb-datawidth: false

        microchip,frame-size: false

        microchip,protocol-configuration: false

        microchip,motorola-mode: false

        microchip,ssel-active: false



unevaluatedProperties: false



examples:

Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt

deleted100644 → 0
+0 −36
Original line number Diff line number Diff line 
Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver



Nuvoton NPCM7xx SOC support two PSPI channels.



Required properties:

 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.

				"nuvoton,npcm845-pspi" for Arbel NPCM8XX.

 - #address-cells : should be 1. see spi-bus.txt

 - #size-cells : should be 0. see spi-bus.txt

 - specifies physical base address and size of the register.

 - interrupts : contain PSPI interrupt.

 - clocks : phandle of PSPI reference clock.

 - clock-names: Should be "clk_apb5".

 - pinctrl-names : a pinctrl state named "default" must be defined.

 - pinctrl-0 : phandle referencing pin configuration of the device.

 - resets : phandle to the reset control for this device.

 - cs-gpios: Specifies the gpio pins to be used for chipselects.

            See: Documentation/devicetree/bindings/spi/spi-bus.txt



Optional properties:

- clock-frequency : Input clock frequency to the PSPI block in Hz.

		    Default is 25000000 Hz.



spi0: spi@f0200000 {

	compatible = "nuvoton,npcm750-pspi";

	reg = <0xf0200000 0x1000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pspi1_pins>;

	#address-cells = <1>;

	#size-cells = <0>;

	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&clk NPCM7XX_CLK_APB5>;

	clock-names = "clk_apb5";

	resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>

	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;

};