Commit fa6b90ee authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/asm' into x86/core, to merge dependent commits 

Prepare to resolve conflicts with an upstream series of fixes that conflict
with pending x86 changes:

  6f5bf947 Merge tag 'its-for-linus-20250509' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip



Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 11d8f542 4b626015

arch/x86/boot/boot.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
extern struct setup_header hdr;

extern struct boot_params boot_params;



#define cpu_relax()	asm volatile("rep; nop")

#define cpu_relax()	asm volatile("pause")



static inline void io_delay(void)

{

arch/x86/include/asm/arch_hweight.h

+2 −4
Original line number Diff line number Diff line
@@ -16,8 +16,7 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w) 
{

	unsigned int res;



	asm_inline (ALTERNATIVE(ANNOTATE_IGNORE_ALTERNATIVE

				"call __sw_hweight32",

	asm_inline (ALTERNATIVE("call __sw_hweight32",

				"popcntl %[val], %[cnt]", X86_FEATURE_POPCNT)

			 : [cnt] "=" REG_OUT (res), ASM_CALL_CONSTRAINT

			 : [val] REG_IN (w));
@@ -46,8 +45,7 @@ static __always_inline unsigned long __arch_hweight64(__u64 w) 
{

	unsigned long res;



	asm_inline (ALTERNATIVE(ANNOTATE_IGNORE_ALTERNATIVE

				"call __sw_hweight64",

	asm_inline (ALTERNATIVE("call __sw_hweight64",

				"popcntq %[val], %[cnt]", X86_FEATURE_POPCNT)

			 : [cnt] "=" REG_OUT (res), ASM_CALL_CONSTRAINT

			 : [val] REG_IN (w));

arch/x86/include/asm/bitops.h

+2 −5
Original line number Diff line number Diff line
@@ -248,7 +248,7 @@ arch_test_bit_acquire(unsigned long nr, const volatile unsigned long *addr) 


static __always_inline unsigned long variable__ffs(unsigned long word)

{

	asm("rep; bsf %1,%0"

	asm("tzcnt %1,%0"

		: "=r" (word)

		: ASM_INPUT_RM (word));

	return word;
@@ -267,10 +267,7 @@ static __always_inline unsigned long variable__ffs(unsigned long word) 


static __always_inline unsigned long variable_ffz(unsigned long word)

{

	asm("rep; bsf %1,%0"

		: "=r" (word)

		: "r" (~word));

	return word;

	return variable__ffs(~word);

}



/**

arch/x86/include/asm/debugreg.h

+6 −6
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ DECLARE_PER_CPU(unsigned long, cpu_dr7); 


static __always_inline unsigned long native_get_debugreg(int regno)

{

	unsigned long val = 0;	/* Damn you, gcc! */

	unsigned long val;



	switch (regno) {

	case 0:
@@ -43,7 +43,7 @@ static __always_inline unsigned long native_get_debugreg(int regno) 
		break;

	case 7:

		/*

		 * Apply __FORCE_ORDER to DR7 reads to forbid re-ordering them

		 * Use "asm volatile" for DR7 reads to forbid re-ordering them

		 * with other code.

		 *

		 * This is needed because a DR7 access can cause a #VC exception
@@ -55,7 +55,7 @@ static __always_inline unsigned long native_get_debugreg(int regno) 
		 * re-ordered to happen before the call to sev_es_ist_enter(),

		 * causing stack recursion.

		 */

		asm volatile("mov %%db7, %0" : "=r" (val) : __FORCE_ORDER);

		asm volatile("mov %%db7, %0" : "=r" (val));

		break;

	default:

		BUG();
@@ -83,15 +83,15 @@ static __always_inline void native_set_debugreg(int regno, unsigned long value) 
		break;

	case 7:

		/*

		 * Apply __FORCE_ORDER to DR7 writes to forbid re-ordering them

		 * Use "asm volatile" for DR7 writes to forbid re-ordering them

		 * with other code.

		 *

		 * While is didn't happen with a DR7 write (see the DR7 read

		 * comment above which explains where it happened), add the

		 * __FORCE_ORDER here too to avoid similar problems in the

		 * "asm volatile" here too to avoid similar problems in the

		 * future.

		 */

		asm volatile("mov %0, %%db7"	::"r" (value), __FORCE_ORDER);

		asm volatile("mov %0, %%db7"	::"r" (value));

		break;

	default:

		BUG();

arch/x86/include/asm/inat.h

+6 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ 
#define INAT_NO_REX2	(1 << (INAT_FLAG_OFFS + 8))

#define INAT_REX2_VARIANT	(1 << (INAT_FLAG_OFFS + 9))

#define INAT_EVEX_SCALABLE	(1 << (INAT_FLAG_OFFS + 10))

#define INAT_INV64	(1 << (INAT_FLAG_OFFS + 11))

/* Attribute making macros for attribute tables */

#define INAT_MAKE_PREFIX(pfx)	(pfx << INAT_PFX_OFFS)

#define INAT_MAKE_ESCAPE(esc)	(esc << INAT_ESC_OFFS)
@@ -242,4 +243,9 @@ static inline int inat_evex_scalable(insn_attr_t attr) 
{

	return attr & INAT_EVEX_SCALABLE;

}



static inline int inat_is_invalid64(insn_attr_t attr)

{

	return attr & INAT_INV64;

}

#endif