Commit fa6e6cd2 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-stmmac-pcs-support-part-2' 

Russell King says:

====================
net: stmmac: pcs support part 2

This is the next part of stmmac PCS support. Not much here, other than
dealing with what remains of the interrupts, which are the PCS AN
complete and PCS Link interrupts, which are just cleared and update
accounting.

Currently, they are enabled at core init time, but if we have an
implementation that supports multiple PHY interfaces, we want to
enable only the appropriate interrupts.

I also noticed that stmmac_fpe_configure_pmac() also modifies the
interrupt mask during run time. As a pre-requisit, we need a way
to ensure that we don't have different threads modifying the
interrupt settings at the same time. So, the first patch introduces
a new function and a spinlock which must be held when manipulating
the interrupt enable/mask state.

The second patch adds the PCS bits for enabling the PCS AN and PCS
link interrupts when the PCS is in-use.
====================

Link: https://patch.msgid.link/aPn5YVeUcWo4CW3c@shell.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 86b66cb8 eed68eda

drivers/net/ethernet/stmicro/stmmac/common.h

+5 −0
Original line number Diff line number Diff line
@@ -611,6 +611,11 @@ struct mac_device_info { 
	u8 vlan_fail_q;

	bool hw_vlan_en;

	bool reverse_sgmii_enable;



	/* This spinlock protects read-modify-write of the interrupt

	 * mask/enable registers.

	 */

	spinlock_t irq_ctrl_lock;

};



struct stmmac_rx_routing {

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+3 −4
Original line number Diff line number Diff line
@@ -38,11 +38,10 @@ 
#define	GMAC_INT_DISABLE_PCSAN		BIT(2)

#define	GMAC_INT_DISABLE_PMT		BIT(3)

#define	GMAC_INT_DISABLE_TIMESTAMP	BIT(9)

#define	GMAC_INT_DISABLE_PCS	(GMAC_INT_DISABLE_PCSLINK | \

				 GMAC_INT_DISABLE_PCSAN)

#define	GMAC_INT_DEFAULT_MASK	(GMAC_INT_DISABLE_RGMII | \

				 GMAC_INT_DISABLE_TIMESTAMP | \

				 GMAC_INT_DISABLE_PCS)

				 GMAC_INT_DISABLE_PCSLINK | \

				 GMAC_INT_DISABLE_PCSAN | \

				 GMAC_INT_DISABLE_TIMESTAMP)



/* PMT Control and Status */

#define GMAC_PMT		0x0000002c

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+19 −7
Original line number Diff line number Diff line
@@ -27,7 +27,9 @@ static int dwmac1000_pcs_init(struct stmmac_priv *priv) 
	if (!priv->dma_cap.pcs)

		return 0;



	return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE);

	return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,

					  GMAC_INT_DISABLE_PCSLINK |

					  GMAC_INT_DISABLE_PCSAN);

}



static void dwmac1000_core_init(struct mac_device_info *hw,
@@ -48,12 +50,7 @@ static void dwmac1000_core_init(struct mac_device_info *hw, 
	writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONTROL);



	/* Mask GMAC interrupts */

	value = GMAC_INT_DEFAULT_MASK;



	if (hw->pcs)

		value &= ~GMAC_INT_DISABLE_PCS;



	writel(value, ioaddr + GMAC_INT_MASK);

	writel(GMAC_INT_DEFAULT_MASK, ioaddr + GMAC_INT_MASK);



#ifdef STMMAC_VLAN_TAG_USED

	/* Tag detection without filtering */
@@ -61,6 +58,20 @@ static void dwmac1000_core_init(struct mac_device_info *hw, 
#endif

}



static void dwmac1000_irq_modify(struct mac_device_info *hw, u32 disable,

				 u32 enable)

{

	void __iomem *int_mask = hw->pcsr + GMAC_INT_MASK;

	unsigned long flags;

	u32 value;



	spin_lock_irqsave(&hw->irq_ctrl_lock, flags);

	value = readl(int_mask) | disable;

	value &= ~enable;

	writel(value, int_mask);

	spin_unlock_irqrestore(&hw->irq_ctrl_lock, flags);

}



static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)

{

	void __iomem *ioaddr = hw->pcsr;
@@ -445,6 +456,7 @@ static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable) 
const struct stmmac_ops dwmac1000_ops = {

	.pcs_init = dwmac1000_pcs_init,

	.core_init = dwmac1000_core_init,

	.irq_modify = dwmac1000_irq_modify,

	.set_mac = stmmac_set_mac,

	.rx_ipc = dwmac1000_rx_ipc_enable,

	.dump_regs = dwmac1000_dump_regs,

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

+0 −2
Original line number Diff line number Diff line
@@ -106,8 +106,6 @@ 
#define GMAC_INT_LPI_EN			BIT(5)

#define GMAC_INT_TSIE			BIT(12)



#define	GMAC_PCS_IRQ_DEFAULT	(GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE)



#define	GMAC_INT_DEFAULT_ENABLE	(GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \

				 GMAC_INT_TSIE)

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

+20 −7
Original line number Diff line number Diff line
@@ -27,7 +27,8 @@ static int dwmac4_pcs_init(struct stmmac_priv *priv) 
	if (!priv->dma_cap.pcs)

		return 0;



	return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE);

	return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,

					  GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE);

}



static void dwmac4_core_init(struct mac_device_info *hw,
@@ -46,17 +47,26 @@ static void dwmac4_core_init(struct mac_device_info *hw, 
	writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);



	/* Enable GMAC interrupts */

	value = GMAC_INT_DEFAULT_ENABLE;



	if (hw->pcs)

		value |= GMAC_PCS_IRQ_DEFAULT;



	writel(value, ioaddr + GMAC_INT_EN);

	writel(GMAC_INT_DEFAULT_ENABLE, ioaddr + GMAC_INT_EN);



	if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)

		init_waitqueue_head(&priv->tstamp_busy_wait);

}



static void dwmac4_irq_modify(struct mac_device_info *hw, u32 disable,

			      u32 enable)

{

	void __iomem *int_mask = hw->pcsr + GMAC_INT_EN;

	unsigned long flags;

	u32 value;



	spin_lock_irqsave(&hw->irq_ctrl_lock, flags);

	value = readl(int_mask) & ~disable;

	value |= enable;

	writel(value, int_mask);

	spin_unlock_irqrestore(&hw->irq_ctrl_lock, flags);

}



static void dwmac4_update_caps(struct stmmac_priv *priv)

{

	if (priv->plat->tx_queues_to_use > 1)
@@ -885,6 +895,7 @@ static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no, 
const struct stmmac_ops dwmac4_ops = {

	.pcs_init = dwmac4_pcs_init,

	.core_init = dwmac4_core_init,

	.irq_modify = dwmac4_irq_modify,

	.update_caps = dwmac4_update_caps,

	.set_mac = stmmac_set_mac,

	.rx_ipc = dwmac4_rx_ipc_enable,
@@ -920,6 +931,7 @@ const struct stmmac_ops dwmac4_ops = { 
const struct stmmac_ops dwmac410_ops = {

	.pcs_init = dwmac4_pcs_init,

	.core_init = dwmac4_core_init,

	.irq_modify = dwmac4_irq_modify,

	.update_caps = dwmac4_update_caps,

	.set_mac = stmmac_dwmac4_set_mac,

	.rx_ipc = dwmac4_rx_ipc_enable,
@@ -957,6 +969,7 @@ const struct stmmac_ops dwmac410_ops = { 
const struct stmmac_ops dwmac510_ops = {

	.pcs_init = dwmac4_pcs_init,

	.core_init = dwmac4_core_init,

	.irq_modify = dwmac4_irq_modify,

	.update_caps = dwmac4_update_caps,

	.set_mac = stmmac_dwmac4_set_mac,

	.rx_ipc = dwmac4_rx_ipc_enable,