Commit fa84f443 authored by David E. Box's avatar David E. Box Committed by Bjorn Helgaas
Browse files

PCI/ASPM: Move pci_configure_ltr() to aspm.c 



The Latency Tolerance Reporting (LTR) mechanism supports the ASPM L1.2
state and is only configured when CONFIG_PCIEASPM is set.

Move pci_configure_ltr() and pci_bridge_reconfigure_ltr() into aspm.c since
they only build when CONFIG_PCIEASPM is set.  No functional change
intended.

Suggested-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20240128233212.1139663-2-david.e.box@linux.intel.com
[bhelgaas: commit log, split build change from function moves]
Link: https://lore.kernel.org/r/20240223205851.114931-2-helgaas@kernel.org


Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 6613476e

drivers/pci/pci.c

+0 −18
Original line number Diff line number Diff line
@@ -1626,24 +1626,6 @@ static int pci_save_pcie_state(struct pci_dev *dev) 
	return 0;

}



void pci_bridge_reconfigure_ltr(struct pci_dev *dev)

{

#ifdef CONFIG_PCIEASPM

	struct pci_dev *bridge;

	u32 ctl;



	bridge = pci_upstream_bridge(dev);

	if (bridge && bridge->ltr_path) {

		pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);

		if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {

			pci_dbg(bridge, "re-enabling LTR\n");

			pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,

						 PCI_EXP_DEVCTL2_LTR_EN);

		}

	}

#endif

}



static void pci_restore_pcie_state(struct pci_dev *dev)

{

	int i = 0;

drivers/pci/pci.h

+4 −1
Original line number Diff line number Diff line
@@ -97,7 +97,6 @@ void pci_msi_init(struct pci_dev *dev); 
void pci_msix_init(struct pci_dev *dev);

bool pci_bridge_d3_possible(struct pci_dev *dev);

void pci_bridge_d3_update(struct pci_dev *dev);

void pci_bridge_reconfigure_ltr(struct pci_dev *dev);

int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);



static inline void pci_wakeup_event(struct pci_dev *dev)
@@ -573,11 +572,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev); 
void pcie_aspm_exit_link_state(struct pci_dev *pdev);

void pcie_aspm_pm_state_change(struct pci_dev *pdev);

void pcie_aspm_powersave_config_link(struct pci_dev *pdev);

void pci_configure_ltr(struct pci_dev *pdev);

void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);

#else

static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }

static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }

static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }

static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }

static inline void pci_configure_ltr(struct pci_dev *pdev) { }

static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }

#endif



#ifdef CONFIG_PCIE_ECRC

drivers/pci/pcie/aspm.c

+75 −0
Original line number Diff line number Diff line
@@ -938,6 +938,81 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev) 
	up_read(&pci_bus_sem);

}



void pci_bridge_reconfigure_ltr(struct pci_dev *pdev)

{

	struct pci_dev *bridge;

	u32 ctl;



	bridge = pci_upstream_bridge(pdev);

	if (bridge && bridge->ltr_path) {

		pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);

		if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {

			pci_dbg(bridge, "re-enabling LTR\n");

			pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,

						 PCI_EXP_DEVCTL2_LTR_EN);

		}

	}

}



void pci_configure_ltr(struct pci_dev *pdev)

{

	struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);

	struct pci_dev *bridge;

	u32 cap, ctl;



	if (!pci_is_pcie(pdev))

		return;



	/* Read L1 PM substate capabilities */

	pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);



	pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap);

	if (!(cap & PCI_EXP_DEVCAP2_LTR))

		return;



	pcie_capability_read_dword(pdev, PCI_EXP_DEVCTL2, &ctl);

	if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {

		if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {

			pdev->ltr_path = 1;

			return;

		}



		bridge = pci_upstream_bridge(pdev);

		if (bridge && bridge->ltr_path)

			pdev->ltr_path = 1;



		return;

	}



	if (!host->native_ltr)

		return;



	/*

	 * Software must not enable LTR in an Endpoint unless the Root

	 * Complex and all intermediate Switches indicate support for LTR.

	 * PCIe r4.0, sec 6.18.

	 */

	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {

		pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,

					 PCI_EXP_DEVCTL2_LTR_EN);

		pdev->ltr_path = 1;

		return;

	}



	/*

	 * If we're configuring a hot-added device, LTR was likely

	 * disabled in the upstream bridge, so re-enable it before enabling

	 * it in the new device.

	 */

	bridge = pci_upstream_bridge(pdev);

	if (bridge && bridge->ltr_path) {

		pci_bridge_reconfigure_ltr(pdev);

		pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,

					 PCI_EXP_DEVCTL2_LTR_EN);

		pdev->ltr_path = 1;

	}

}



/* Recheck latencies and update aspm_capable for links under the root */

static void pcie_update_aspm_capable(struct pcie_link_state *root)

{

drivers/pci/probe.c

+0 −61
Original line number Diff line number Diff line
@@ -2209,67 +2209,6 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) 
	}

}



static void pci_configure_ltr(struct pci_dev *dev)

{

#ifdef CONFIG_PCIEASPM

	struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);

	struct pci_dev *bridge;

	u32 cap, ctl;



	if (!pci_is_pcie(dev))

		return;



	/* Read L1 PM substate capabilities */

	dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);



	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);

	if (!(cap & PCI_EXP_DEVCAP2_LTR))

		return;



	pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);

	if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {

		if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {

			dev->ltr_path = 1;

			return;

		}



		bridge = pci_upstream_bridge(dev);

		if (bridge && bridge->ltr_path)

			dev->ltr_path = 1;



		return;

	}



	if (!host->native_ltr)

		return;



	/*

	 * Software must not enable LTR in an Endpoint unless the Root

	 * Complex and all intermediate Switches indicate support for LTR.

	 * PCIe r4.0, sec 6.18.

	 */

	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {

		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,

					 PCI_EXP_DEVCTL2_LTR_EN);

		dev->ltr_path = 1;

		return;

	}



	/*

	 * If we're configuring a hot-added device, LTR was likely

	 * disabled in the upstream bridge, so re-enable it before enabling

	 * it in the new device.

	 */

	bridge = pci_upstream_bridge(dev);

	if (bridge && bridge->ltr_path) {

		pci_bridge_reconfigure_ltr(dev);

		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,

					 PCI_EXP_DEVCTL2_LTR_EN);

		dev->ltr_path = 1;

	}

#endif

}



static void pci_configure_eetlp_prefix(struct pci_dev *dev)

{

#ifdef CONFIG_PCI_PASID