Unverified Commit faceb344 authored by Rander Wang's avatar Rander Wang Committed by Mark Brown
Browse files

ASoC: SOF: Intel: mtl: add get_stream_position support 



Get HDaudio link position for current stream delay calculation
from hda registers.

Signed-off-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230202132954.26773-9-peter.ujfalusi@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7f956297

sound/soc/sof/intel/mtl.c

+14 −0
Original line number Diff line number Diff line
@@ -581,6 +581,18 @@ static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 
	return mtl_enable_interrupts(sdev, false);

}



static u64 mtl_dsp_get_stream_hda_link_position(struct snd_sof_dev *sdev,

						struct snd_soc_component *component,

						struct snd_pcm_substream *substream)

{

	struct hdac_stream *hstream = substream->runtime->private_data;

	u32 llp_l, llp_u;



	llp_l = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPL(hstream->index));

	llp_u = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPU(hstream->index));

	return ((u64)llp_u << 32) | llp_l;

}



/* Meteorlake ops */

struct snd_sof_dsp_ops sof_mtl_ops;

EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
@@ -619,6 +631,8 @@ int sof_mtl_ops_init(struct snd_sof_dev *sdev) 
	/* dsp core get/put */

	/* TODO: add core_get and core_put */



	sof_mtl_ops.get_stream_position = mtl_dsp_get_stream_hda_link_position;



	sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);

	if (!sdev->private)

		return -ENOMEM;

sound/soc/sof/intel/mtl.h

+6 −0
Original line number Diff line number Diff line
@@ -6,6 +6,12 @@ 
 * Copyright(c) 2020-2022 Intel Corporation. All rights reserved.

 */



/* HDA Registers */

#define MTL_PPLCLLPL_BASE		0x948

#define MTL_PPLCLLPU_STRIDE		0x10

#define MTL_PPLCLLPL(x)			(MTL_PPLCLLPL_BASE + (x) * MTL_PPLCLLPU_STRIDE)

#define MTL_PPLCLLPU(x)			(MTL_PPLCLLPL_BASE + 0x4 + (x) * MTL_PPLCLLPU_STRIDE)



/* DSP Registers */

#define MTL_HFDSSCS			0x1000

#define MTL_HFDSSCS_SPA_MASK		BIT(16)