Commit faddad52 authored by Dzmitry Sankouski's avatar Dzmitry Sankouski Committed by Bjorn Andersson
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clk: qcom: clk-rcg2: split __clk_rcg2_configure function 



__clk_rcg2_configure function does 2 things -
configures parent and mnd values. In order to
be able to add new clock options, we should split.

Move __clk_rcg2_configure logic on 2 functions:
- __clk_rcg2_configure_parent which configures clock parent
- __clk_rcg2_configure_mnd which configures mnd values

__clk_rcg2_configure delegates to mentioned functions.

Signed-off-by: default avatarDzmitry Sankouski <dsankouski@gmail.com>
Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-2-ac8e36a3aa65@gmail.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent cef0523d

drivers/clk/qcom/clk-rcg2.c

+31 −6
Original line number Diff line number Diff line
@@ -402,16 +402,26 @@ static int clk_rcg2_fm_determine_rate(struct clk_hw *hw, 
	return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req);

}



static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,

				u32 *_cfg)

static int __clk_rcg2_configure_parent(struct clk_rcg2 *rcg, u8 src, u32 *_cfg)

{

	u32 cfg, mask, d_val, not2d_val, n_minus_m;

	struct clk_hw *hw = &rcg->clkr.hw;

	int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);

	int index = qcom_find_src_index(hw, rcg->parent_map, src);



	if (index < 0)

		return index;



	*_cfg &= ~CFG_SRC_SEL_MASK;

	*_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;



	return 0;

}



static int __clk_rcg2_configure_mnd(struct clk_rcg2 *rcg, const struct freq_tbl *f,

				u32 *_cfg)

{

	u32 cfg, mask, d_val, not2d_val, n_minus_m;

	int ret;



	if (rcg->mnd_width && f->n) {

		mask = BIT(rcg->mnd_width) - 1;

		ret = regmap_update_bits(rcg->clkr.regmap,
@@ -440,9 +450,8 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, 
	}



	mask = BIT(rcg->hid_width) - 1;

	mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;

	mask |= CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;

	cfg = f->pre_div << CFG_SRC_DIV_SHIFT;

	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;

	if (rcg->mnd_width && f->n && (f->m != f->n))

		cfg |= CFG_MODE_DUAL_EDGE;

	if (rcg->hw_clk_ctrl)
@@ -454,6 +463,22 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, 
	return 0;

}



static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,

				u32 *_cfg)

{

	int ret;



	ret = __clk_rcg2_configure_parent(rcg, f->src, _cfg);

	if (ret)

		return ret;



	ret = __clk_rcg2_configure_mnd(rcg, f, _cfg);

	if (ret)

		return ret;



	return 0;

}



static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)

{

	u32 cfg;