Commit faeab166 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "Core changes:

   - Perform basic checks on pin config properties so as not to allow
     directly contradictory settings such as setting a pin to more than
     one bias or drive mode

   - Handle input-threshold-voltage-microvolt property

   - Introduce pinctrl_gpio_get_config() handling in the core for SCMI
     GPIO using pin control

  New drivers:

   - GPIO-by-pin control driver (also appearing in the GPIO pull
     request) fulfilling a promise on a comment from Grant Likely many
     years ago: "can't GPIO just be a front-end for pin control?" it
     turns out it can, if and only if you design something new from
     scratch, such as SCMI

   - Broadcom BCM7038 as a pinctrl-single delegate

   - Mobileye EyeQ6Lplus OLB pin controller

   - Qualcomm Eliza and Hawi families TLMM pin controllers

   - Qualcomm SDM670 and Milos family LPASS LPI pin controllers

   - Qualcomm IPQ5210 pin controller

   - Realtek RTD1625 pin controller support

   - Rockchip RV1103B pin controller support

   - Texas Instruments AM62L as a pinctrl-single delegate

  Improvements:

   - Set config implementation for the Spacemit K1 pin controller"

* tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (84 commits)
  pinctrl: qcom: Add Hawi pinctrl driver
  dt-bindings: pinctrl: qcom: Describe Hawi TLMM block
  dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema
  pinctrl: single: Add bcm7038-padconf compatible matching
  dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf
  dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible
  pinctrl: qcom: sdm670-lpass-lpi: label variables as static
  pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description
  pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description
  pinctrl: qcom: add sdm670 lpi tlmm
  dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl
  dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property
  pinctrl: qcom: Introduce IPQ5210 TLMM driver
  dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
  pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs
  pinctrl: qcom: eliza: Fix interrupt target bit
  pinctrl: core: Don't use "proxy" headers
  pinctrl: amd: Support new ACPI ID AMDI0033
  pinctrl: renesas: rzg2l: Drop superfluous blank line
  pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers
  ...
parents 401b0e0b 90700e10

Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml

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@@ -18,7 +18,9 @@ properties: 
  compatible:

    oneOf:

      - items:

          - const: apple,t6020-pinctrl

          - enum:

              - apple,t6020-pinctrl

              - apple,t8122-pinctrl

          - const: apple,t8103-pinctrl

      - items:

          # Do not add additional SoC to this list.

Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX1/i.MX25/i.MX27 IOMUX Controller



maintainers:

  - Frank Li <Frank.Li@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    enum:

      - fsl,imx1-iomuxc

      - fsl,imx27-iomuxc



  reg:

    maxItems: 1



  '#address-cells':

    const: 1



  '#size-cells':

    const: 1



  ranges: true



patternProperties:

  '^gpio@[0-9a-f]+$':

    type: object

    $ref: /schemas/gpio/fsl-imx-gpio.yaml

    unevaluatedProperties: false



  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          three integers array, represents a group of pins mux and config

          setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description:

                PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32

                configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN

                is the pin number on the specific port (between 0 and 31)

            - description: |

                MUX_ID is function + (direction << 2) + (gpio_oconf << 4)

                + (gpio_iconfa << 8) + (gpio_iconfb << 10)



                function value is used to select the pin function.

                Possible values:

                  0 - Primary function

                  1 - Alternate function

                  2 - GPIO

                Registers: GIUS (GPIO In Use), GPR (General Purpose Register)



                direction defines the data direction of the pin.

                Possible values:

                  0 - Input

                  1 - Output

                Register: DDIR



                gpio_oconf configures the gpio submodule output signal.

                This does not have any effect unless GPIO function is

                selected. A/B/C_IN are output signals of function blocks

                A,B and C. Specific function blocks are described in the

                reference manual.

                Possible values:

                  0 - A_IN

                  1 - B_IN

                  2 - C_IN

                  3 - Data Register

                Registers: OCR1, OCR2



                gpio_iconfa/b configures the gpio submodule input to

                functionblocks A and B. GPIO function should be selected if

                this is configured.

                Possible values:

                  0 - GPIO_IN

                  1 - Interrupt Status Register

                  2 - Pulldown

                  3 - Pullup

                Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2



            - description:

                CONFIG can be 0 or 1, meaning Pullup disable/enable.

    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



allOf:

  - $ref: pinctrl.yaml#



unevaluatedProperties: false



examples:

  - |

    pinmux@10015000 {

        compatible = "fsl,imx27-iomuxc";

        reg = <0x10015000 0x600>;



        uartgrp {

            fsl,pins = <

                0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */

                0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */

                0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */

                0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */

            >;

        };

    };

Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt

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* Freescale IMX27 IOMUX Controller



Required properties:

- compatible: "fsl,imx27-iomuxc"



The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.



Required properties for pin configuration node:

- fsl,pins: three integers array, represents a group of pins mux and config

  setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.



  PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable

  configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin

  number on the specific port (between 0 and 31).



  MUX_ID is

    function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)



      function value is used to select the pin function.

      Possible values:

          0 - Primary function

          1 - Alternate function

          2 - GPIO

      Registers: GIUS (GPIO In Use), GPR (General Purpose Register)



      direction defines the data direction of the pin.

      Possible values:

          0 - Input

          1 - Output

      Register: DDIR



      gpio_oconf configures the gpio submodule output signal. This does not

      have any effect unless GPIO function is selected. A/B/C_IN are output

      signals of function blocks A,B and C. Specific function blocks are

      described in the reference manual.

      Possible values:

          0 - A_IN

          1 - B_IN

          2 - C_IN

          3 - Data Register

      Registers: OCR1, OCR2



      gpio_iconfa/b configures the gpio submodule input to functionblocks A and

      B. GPIO function should be selected if this is configured.

      Possible values:

          0 - GPIO_IN

          1 - Interrupt Status Register

          2 - Pulldown

          3 - Pullup

      Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2



  CONFIG can be 0 or 1, meaning Pullup disable/enable.





The iomux controller has gpio child nodes which are embedded in the iomux

control registers. They have to be defined as child nodes of the iomux device

node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"

properties for the iomux device node are required.



Example:



iomuxc: iomuxc@10015000 {

	compatible = "fsl,imx27-iomuxc";

	reg = <0x10015000 0x600>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;



	gpio1: gpio@10015000 {

		...

	};



	...



	uart {

		pinctrl_uart1: uart-1 {

			fsl,pins = <

				0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */

				0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */

				0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */

				0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */

			>;

		};



		...

	};

};





For convenience there are macros defined in imx27-pinfunc.h which provide PIN

and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names

are defined in the i.MX27 reference manual.



The above example using macros:



iomuxc: iomuxc@10015000 {

	compatible = "fsl,imx27-iomuxc";

	reg = <0x10015000 0x600>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;



	gpio1: gpio@10015000 {

		...

	};



	...



	uart {

		pinctrl_uart1: uart-1 {

			fsl,pins = <

				MX27_PAD_UART1_TXD__UART1_TXD 0x0

				MX27_PAD_UART1_RXD__UART1_RXD 0x0

				MX27_PAD_UART1_CTS__UART1_CTS 0x0

				MX27_PAD_UART1_RTS__UART1_RTS 0x0

			>;

		};



		...

	};

};

Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml

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@@ -20,6 +20,7 @@ properties: 
  compatible:

    oneOf:

      - enum:

          - fsl,imx25-iomuxc

          - fsl,imx35-iomuxc

          - fsl,imx51-iomuxc

          - fsl,imx53-iomuxc

Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml

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@@ -84,10 +84,11 @@ patternProperties: 


    properties:

      groups:

        items:

          enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,

                  pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,

                ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,

                spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,

                  ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb,

                  smi, spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,

                  usb2_drvvbus1, usb32_drvvbus0 ]



      function: