Commit faebbc58 authored by Babu Moger's avatar Babu Moger Committed by Borislav Petkov (AMD)
Browse files

x86/resctrl: Add support to enable/disable AMD ABMC feature 



Add the functionality to enable/disable the AMD ABMC feature.

The AMD ABMC feature is enabled by setting enabled bit(0) in the
L3_QOS_EXT_CFG MSR. When the state of ABMC is changed, the MSR needs to be
updated on all the logical processors in the QOS Domain.

Hardware counters will reset when ABMC state is changed.

  [ bp: Massage commit message. ]

Signed-off-by: default avatarBabu Moger <babu.moger@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
parent 13390861

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -1223,6 +1223,7 @@ 
/* - AMD: */

#define MSR_IA32_MBA_BW_BASE		0xc0000200

#define MSR_IA32_SMBA_BW_BASE		0xc0000280

#define MSR_IA32_L3_QOS_EXT_CFG		0xc00003ff

#define MSR_IA32_EVT_CFG_BASE		0xc0000400



/* AMD-V MSRs */

arch/x86/kernel/cpu/resctrl/internal.h

+5 −0
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ struct arch_mbm_state { 
	u64	prev_msr;

};



/* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */

#define ABMC_ENABLE_BIT			0



/**

 * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share

 *			       a resource for a control function
@@ -102,6 +105,7 @@ struct msr_param { 
 * @mon_scale:		cqm counter * mon_scale = occupancy in bytes

 * @mbm_width:		Monitor width, to detect and correct for overflow.

 * @cdp_enabled:	CDP state of this resource

 * @mbm_cntr_assign_enabled:	ABMC feature is enabled

 *

 * Members of this structure are either private to the architecture

 * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
@@ -115,6 +119,7 @@ struct rdt_hw_resource { 
	unsigned int		mon_scale;

	unsigned int		mbm_width;

	bool			cdp_enabled;

	bool			mbm_cntr_assign_enabled;

};



static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)

arch/x86/kernel/cpu/resctrl/monitor.c

+45 −0
Original line number Diff line number Diff line
@@ -399,3 +399,48 @@ void __init intel_rdt_mbm_apply_quirk(void) 
	mbm_cf_rmidthreshold = mbm_cf_table[cf_index].rmidthreshold;

	mbm_cf = mbm_cf_table[cf_index].cf;

}



static void resctrl_abmc_set_one_amd(void *arg)

{

	bool *enable = arg;



	if (*enable)

		msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);

	else

		msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);

}



/*

 * ABMC enable/disable requires update of L3_QOS_EXT_CFG MSR on all the CPUs

 * associated with all monitor domains.

 */

static void _resctrl_abmc_enable(struct rdt_resource *r, bool enable)

{

	struct rdt_mon_domain *d;



	lockdep_assert_cpus_held();



	list_for_each_entry(d, &r->mon_domains, hdr.list) {

		on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_abmc_set_one_amd,

				 &enable, 1);

		resctrl_arch_reset_rmid_all(r, d);

	}

}



int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable)

{

	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);



	if (r->mon.mbm_cntr_assignable &&

	    hw_res->mbm_cntr_assign_enabled != enable) {

		_resctrl_abmc_enable(r, enable);

		hw_res->mbm_cntr_assign_enabled = enable;

	}



	return 0;

}



bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r)

{

	return resctrl_to_arch_res(r)->mbm_cntr_assign_enabled;

}

include/linux/resctrl.h

+20 −0
Original line number Diff line number Diff line
@@ -445,6 +445,26 @@ static inline u32 resctrl_get_config_index(u32 closid, 
bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l);

int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable);



/**

 * resctrl_arch_mbm_cntr_assign_enabled() - Check if MBM counter assignment

 *					    mode is enabled.

 * @r:		Pointer to the resource structure.

 *

 * Return:

 * true if the assignment mode is enabled, false otherwise.

 */

bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r);



/**

 * resctrl_arch_mbm_cntr_assign_set() - Configure the MBM counter assignment mode.

 * @r:		Pointer to the resource structure.

 * @enable:	Set to true to enable, false to disable the assignment mode.

 *

 * Return:

 * 0 on success, < 0 on error.

 */

int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable);



/*

 * Update the ctrl_val and apply this config right now.

 * Must be called on one of the domain's CPUs.