Commit faf66a71 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-fixes-2025-11-06' of... 

Merge tag 'drm-misc-fixes-2025-11-06' of https://gitlab.freedesktop.org/drm/misc/kernel

 into drm-fixes

Short summary of fixes pull:

imagination:
- kconfig: Fix dependencies

nouveau:
- Set DMA mask earlier
- Advertize correct modifiers for GB20x

pixpaper:
- kconfig: Fix dependencies

sched:
- Fix deadlock

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20251106131244.GA155679@2a02-2454-fd5e-fd00-d540-1fd5-75b4-d5e2.dyn6.pyur.net
parents 6146a0f1 b750f5a9

drivers/gpu/drm/imagination/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ config DRM_POWERVR 
	depends on DRM

	depends on MMU

	depends on PM

	depends on POWER_SEQUENCING || !POWER_SEQUENCING

	select DRM_EXEC

	select DRM_GEM_SHMEM_HELPER

	select DRM_SCHED

drivers/gpu/drm/nouveau/dispnv50/disp.c

+3 −1
Original line number Diff line number Diff line
@@ -2867,7 +2867,9 @@ nv50_display_create(struct drm_device *dev) 
	}



	/* Assign the correct format modifiers */

	if (disp->disp->object.oclass >= TU102_DISP)

	if (disp->disp->object.oclass >= GB202_DISP)

		nouveau_display(dev)->format_modifiers = wndwca7e_modifiers;

	else if (disp->disp->object.oclass >= TU102_DISP)

		nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;

	else

	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)

drivers/gpu/drm/nouveau/dispnv50/disp.h

+1 −0
Original line number Diff line number Diff line
@@ -104,4 +104,5 @@ struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder); 
extern const u64 disp50xx_modifiers[];

extern const u64 disp90xx_modifiers[];

extern const u64 wndwc57e_modifiers[];

extern const u64 wndwca7e_modifiers[];

#endif

drivers/gpu/drm/nouveau/dispnv50/wndw.c

+22 −2
Original line number Diff line number Diff line
@@ -786,13 +786,14 @@ nv50_wndw_destroy(struct drm_plane *plane) 
}



/* This function assumes the format has already been validated against the plane

 * and the modifier was validated against the device-wides modifier list at FB

 * and the modifier was validated against the device-wide modifier list at FB

 * creation time.

 */

static bool nv50_plane_format_mod_supported(struct drm_plane *plane,

					    u32 format, u64 modifier)

{

	struct nouveau_drm *drm = nouveau_drm(plane->dev);

	const struct drm_format_info *info = drm_format_info(format);

	uint8_t i;



	/* All chipsets can display all formats in linear layout */
@@ -800,13 +801,32 @@ static bool nv50_plane_format_mod_supported(struct drm_plane *plane, 
		return true;



	if (drm->client.device.info.chipset < 0xc0) {

		const struct drm_format_info *info = drm_format_info(format);

		const uint8_t kind = (modifier >> 12) & 0xff;



		if (!format) return false;



		for (i = 0; i < info->num_planes; i++)

			if ((info->cpp[i] != 4) && kind != 0x70) return false;

	} else if (drm->client.device.info.chipset >= 0x1b2) {

		const uint8_t slayout = ((modifier >> 22) & 0x1) |

			((modifier >> 25) & 0x6);



		if (!format)

			return false;



		/*

		 * Note in practice this implies only formats where cpp is equal

		 * for each plane, or >= 4 for all planes, are supported.

		 */

		for (i = 0; i < info->num_planes; i++) {

			if (((info->cpp[i] == 2) && slayout != 3) ||

			    ((info->cpp[i] == 1) && slayout != 2) ||

			    ((info->cpp[i] >= 4) && slayout != 1))

				return false;



			/* 24-bit not supported. It has yet another layout */

			WARN_ON(info->cpp[i] == 3);

		}

	}



	return true;

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

+33 −0
Original line number Diff line number Diff line
@@ -179,6 +179,39 @@ wndwca7e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 
	return 0;

}



/****************************************************************

 *            Log2(block height) ----------------------------+  *

 *            Page Kind ----------------------------------+  |  *

 *            Gob Height/Page Kind Generation ------+     |  |  *

 *                          Sector layout -------+  |     |  |  *

 *                          Compression ------+  |  |     |  |  */

const u64 wndwca7e_modifiers[] = { /*         |  |  |     |  |  */

	/* 4cpp+ modifiers */

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 0),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 1),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 2),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 3),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 4),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 5),

	/* 1cpp/8bpp modifiers */

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 0),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 1),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 2),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 3),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 4),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 5),

	/* 2cpp/16bpp modifiers */

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 0),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 1),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 2),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 3),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 4),

	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 5),

	/* All formats support linear */

	DRM_FORMAT_MOD_LINEAR,

	DRM_FORMAT_MOD_INVALID

};



static const struct nv50_wndw_func

wndwca7e = {

	.acquire = wndwc37e_acquire,