Commit fb01ab52 authored by Fangzhi Zuo's avatar Fangzhi Zuo Committed by Alex Deucher
Browse files

drm/amd/display: Populate dtbclk from bounding box 



dtbclk is unavaliable from pmfw. Try to grab the value from bounding box

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a409c053

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

+9 −5
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { 
			.phyclk_mhz = 600.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 186.0,

			.dtbclk_mhz = 625.0,

			.dtbclk_mhz = 600.0,

		},

		{

			.state = 1,
@@ -133,7 +133,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { 
			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 209.0,

			.dtbclk_mhz = 625.0,

			.dtbclk_mhz = 600.0,

		},

		{

			.state = 2,
@@ -142,7 +142,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { 
			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 209.0,

			.dtbclk_mhz = 625.0,

			.dtbclk_mhz = 600.0,

		},

		{

			.state = 3,
@@ -151,7 +151,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { 
			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 371.0,

			.dtbclk_mhz = 625.0,

			.dtbclk_mhz = 600.0,

		},

		{

			.state = 4,
@@ -160,7 +160,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { 
			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 417.0,

			.dtbclk_mhz = 625.0,

			.dtbclk_mhz = 600.0,

		},

	},

	.num_states = 5,
@@ -348,6 +348,8 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, 
				clock_limits[i].socclk_mhz;

			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

				clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;

			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

				clock_limits[i].dtbclk_mhz;

			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

				clk_table->num_entries;

			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
@@ -360,6 +362,8 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, 
				clk_table->num_entries;

			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

				clk_table->num_entries;

			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

				clk_table->num_entries;

		}

	}

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

+3 −2
Original line number Diff line number Diff line
@@ -423,6 +423,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, 
		}



		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {

			if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0)

				p->in_states->state_array[i].dtbclk_mhz =

					dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;

		}