Commit fb091ff3 authored by Easwar Hariharan's avatar Easwar Hariharan Committed by Will Deacon
Browse files

arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata 



Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
suffers from all the same errata.

CC: stable@vger.kernel.org # 5.15+
Signed-off-by: default avatarEaswar Hariharan <eahariha@linux.microsoft.com>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarOliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240214175522.2457857-1-eahariha@linux.microsoft.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 50572064

Documentation/arch/arm64/silicon-errata.rst

+7 −0
Original line number Diff line number Diff line
@@ -243,3 +243,10 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ASR            | ASR8601         | #8601001        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2139208        | ARM64_ERRATUM_2139208       |

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2067961        | ARM64_ERRATUM_2067961       |

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ 
#define ARM_CPU_IMP_HISI		0x48

#define ARM_CPU_IMP_APPLE		0x61

#define ARM_CPU_IMP_AMPERE		0xC0

#define ARM_CPU_IMP_MICROSOFT		0x6D



#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00
@@ -135,6 +136,8 @@ 


#define AMPERE_CPU_PART_AMPERE1		0xAC3



#define MICROSOFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -193,6 +196,7 @@ 
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)

#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)

#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

arch/arm64/kernel/cpu_errata.c

+3 −0
Original line number Diff line number Diff line
@@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = { 
static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_2139208

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

	MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2119858

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 
static const struct midr_range tsb_flush_fail_cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_2067961

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

	MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2054223

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = { 
static struct midr_range trbe_write_out_of_range_cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_2253138

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

	MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2224489

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),