Commit fb797a70 authored by Chris Brandt's avatar Chris Brandt Committed by Biju Das
Browse files

drm: renesas: rz-du: mipi_dsi: Set DSI divider 



Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be set.

Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Tested-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Fixes: 5a4326f2 ("clk: renesas: rzg2l: Remove DSI clock rate restrictions")
Link: https://patch.msgid.link/20260227015216.2721504-1-chris.brandt@renesas.com


Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
parent 89ff4535

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

+15 −1
Original line number Diff line number Diff line
@@ -1122,6 +1122,7 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
				      struct mipi_dsi_device *device)

{

	struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);

	int bpp;

	int ret;



	if (device->lanes > dsi->num_data_lanes) {
@@ -1131,7 +1132,8 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
		return -EINVAL;

	}



	switch (mipi_dsi_pixel_format_to_bpp(device->format)) {

	bpp = mipi_dsi_pixel_format_to_bpp(device->format);

	switch (bpp) {

	case 24:

		break;

	case 18:
@@ -1162,6 +1164,18 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, 


	drm_bridge_add(&dsi->bridge);



	/*

	 * Report the required division ratio setting for the MIPI clock dividers.

	 *

	 * vclk * bpp = hsclk * 8 * num_lanes

	 *

	 * vclk * DSI_AB_divider = hsclk * 16

	 *

	 *   which simplifies to...

	 * DSI_AB_divider = bpp * 2 / num_lanes

	 */

	rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, PLL5_TARGET_DSI);



	return 0;

}