Commit fbbbb621 authored by Sunil Khatri's avatar Sunil Khatri Committed by Alex Deucher
Browse files

drm/amdgpu: add gfx12 register support in ipdump 



Add general registers of gfx12 in ipdump for
devcoredump support.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ffcc5745

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+101 −0
Original line number Diff line number Diff line
@@ -63,6 +63,73 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 
MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");

MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");



static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),

	SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),

	SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),

	SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),

	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),

	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),



	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	/* SE status registers */

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)

};



#define DEFAULT_SH_MEM_CONFIG \

	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -1129,6 +1196,20 @@ static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 
	return 0;

}



static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)

{

	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);

	uint32_t *ptr;



	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);

	if (ptr == NULL) {

		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");

		adev->gfx.ip_dump_core = NULL;

	} else {

		adev->gfx.ip_dump_core = ptr;

	}

}



static int gfx_v12_0_sw_init(void *handle)

{

	int i, j, k, r, ring_id = 0;
@@ -1261,6 +1342,8 @@ static int gfx_v12_0_sw_init(void *handle) 
	if (r)

		return r;



	gfx_v12_0_alloc_ip_dump(adev);



	return 0;

}
@@ -1320,6 +1403,8 @@ static int gfx_v12_0_sw_fini(void *handle) 


	gfx_v12_0_free_microcode(adev);



	kfree(adev->gfx.ip_dump_core);



	return 0;

}
@@ -4671,6 +4756,21 @@ static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */

}



static void gfx_v12_ip_dump(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	uint32_t i;

	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);



	if (!adev->gfx.ip_dump_core)

		return;



	amdgpu_gfx_off_ctrl(adev, false);

	for (i = 0; i < reg_count; i++)

		adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));

	amdgpu_gfx_off_ctrl(adev, true);

}



static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {

	.name = "gfx_v12_0",

	.early_init = gfx_v12_0_early_init,
@@ -4686,6 +4786,7 @@ static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 
	.set_clockgating_state = gfx_v12_0_set_clockgating_state,

	.set_powergating_state = gfx_v12_0_set_powergating_state,

	.get_clockgating_state = gfx_v12_0_get_clockgating_state,

	.dump_ip_state = gfx_v12_ip_dump,

};



static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {