Commit fbf1035b authored by Mario Limonciello's avatar Mario Limonciello Committed by Alex Deucher
Browse files

drm/amd: Disable PP_PCIE_DPM_MASK when dynamic speed switching not supported 



Rather than individual ASICs checking for the quirk, set the quirk at the
driver level.

Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 541c341d

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −0
Original line number Diff line number Diff line
@@ -2315,6 +2315,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;

	if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)

		adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;

	if (!amdgpu_device_pcie_dynamic_switching_supported())

		adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;



	total = true;

	for (i = 0; i < adev->num_ip_blocks; i++) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

+1 −3
Original line number Diff line number Diff line
@@ -1823,9 +1823,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 


	data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;

	data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;

	data->pcie_dpm_key_disabled =

		!amdgpu_device_pcie_dynamic_switching_supported() ||

		!(hwmgr->feature_mask & PP_PCIE_DPM_MASK);

	data->pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);

	/* need to set voltage control types before EVV patching */

	data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;

	data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+1 −1
Original line number Diff line number Diff line
@@ -2115,7 +2115,7 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 
	min_lane_width = min_lane_width > max_lane_width ?

			 max_lane_width : min_lane_width;



	if (!amdgpu_device_pcie_dynamic_switching_supported()) {

	if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {

		pcie_table->pcie_gen[0] = max_gen_speed;

		pcie_table->pcie_lane[0] = max_lane_width;

	} else {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

+1 −1
Original line number Diff line number Diff line
@@ -2438,7 +2438,7 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu, 
	uint32_t smu_pcie_arg;

	int ret, i;



	if (!amdgpu_device_pcie_dynamic_switching_supported()) {

	if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {

		if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)

			pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];