Unverified Commit fc078ea3 authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
Browse files

riscv: hwprobe: export Zcmop ISA extension 



Export Zcmop ISA extension through hwprobe.

Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Reviewed-by: default avatarEvan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20240619113529.676940-15-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 164d6440

Documentation/arch/riscv/hwprobe.rst

+4 −0
Original line number Diff line number Diff line
@@ -231,6 +231,10 @@ The following keys are defined: 
       ("Zcf doesn't exist on RV64 as it contains no instructions") of

       riscv-code-size-reduction.



  * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is

       supported as defined in the RISC-V ISA manual starting from commit

       c732a4f39a4 ("Zcmop is ratified/1.0").



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZCB		(1ULL << 44)

#define		RISCV_HWPROBE_EXT_ZCD		(1ULL << 45)

#define		RISCV_HWPROBE_EXT_ZCF		(1ULL << 46)

#define		RISCV_HWPROBE_EXT_ZCMOP		(1ULL << 47)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_hwprobe.c

+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZIMOP);

		EXT_KEY(ZCA);

		EXT_KEY(ZCB);

		EXT_KEY(ZCMOP);



		/*

		 * All the following extensions must depend on the kernel