Commit fc6c8af6 authored by Jacky Chou's avatar Jacky Chou Committed by Jakub Kicinski
Browse files

dt-bindings: net: ftgmac100: Add resets property 



In Aspeed AST2600 design, the MAC internal delay on MAC register cannot
fully reset the RMII interfaces, it may cause the RMII incompletely.
Therefore, we need to add resets property to do SoC-level reset line to
reset the whole MAC function that includes ftgmac, RGMII and RMII.

Signed-off-by: default avatarJacky Chou <jacky_chou@aspeedtech.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250709070809.2560688-2-jacky_chou@aspeedtech.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 380a8891

Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml

+18 −3
Original line number Diff line number Diff line
@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 


title: Faraday Technology FTGMAC100 gigabit ethernet controller



allOf:

  - $ref: ethernet-controller.yaml#



maintainers:

  - Po-Yu Chuang <ratbert@faraday-tech.com>
@@ -35,6 +32,9 @@ properties: 
      - description: MAC IP clock

      - description: RMII RCLK gate for AST2500/2600



  resets:

    maxItems: 1



  clock-names:

    minItems: 1

    items:
@@ -74,6 +74,21 @@ required: 
  - reg

  - interrupts



allOf:

  - $ref: ethernet-controller.yaml#

  - if:

      properties:

        compatible:

          contains:

            enum:

              - aspeed,ast2600-mac

    then:

      properties:

        resets: true

    else:

      properties:

        resets: false



unevaluatedProperties: false



examples: