Commit fc6e29d4 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets 



The MDSS resets have so far been left undescribed. Fix that.

Fixes: 75616da7 ("dt-bindings: clock: Introduce QCOM sc7180 display clock bindings")
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710
Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 6de23f81

include/dt-bindings/clock/qcom,dispcc-sc7180.h

+6 −1
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H



/* Clocks */

#define DISP_CC_PLL0				0

#define DISP_CC_PLL0_OUT_EVEN			1

#define DISP_CC_MDSS_AHB_CLK			2
@@ -40,7 +41,11 @@ 
#define DISP_CC_MDSS_VSYNC_CLK_SRC		31

#define DISP_CC_XO_CLK				32



/* DISP_CC GDSCR */

/* Resets */

#define DISP_CC_MDSS_CORE_BCR			0

#define DISP_CC_MDSS_RSCC_BCR			1



/* GDSCs */

#define MDSS_GDSC				0



#endif