Commit fc8fc81c authored by Mitul Golani's avatar Mitul Golani Committed by Suraj Kandpal
Browse files

drm/i915: Update indentation for VRR registers and bits 



Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.

--v2:
- Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit).
- Fix all indentation related VRR registers and bits instead of
checkpatch one.

Signed-off-by: default avatarMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-2-mitulkumar.ajitkumar.golani@intel.com
parent 76dbc416

drivers/gpu/drm/i915/i915_reg.h

+87 −87
Original line number Diff line number Diff line
@@ -1186,10 +1186,10 @@ 
#define  VRR_VMAXSHIFT_DEC			REG_BIT(16)

#define  VRR_VMAXSHIFT_INC_MASK			REG_GENMASK(12, 0)



#define _TRANS_VRR_STATUS_A		0x6042C

#define _TRANS_VRR_STATUS_B		0x6142C

#define _TRANS_VRR_STATUS_C		0x6242C

#define _TRANS_VRR_STATUS_D		0x6342C

#define _TRANS_VRR_STATUS_A			0x6042c

#define _TRANS_VRR_STATUS_B			0x6142c

#define _TRANS_VRR_STATUS_C			0x6242c

#define _TRANS_VRR_STATUS_D			0x6342c

#define TRANS_VRR_STATUS(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)

#define  VRR_STATUS_VMAX_REACHED		REG_BIT(31)

#define  VRR_STATUS_NOFLIP_TILL_BNDR		REG_BIT(30)
@@ -1225,17 +1225,17 @@ 
						_TRANS_VRR_FLIPLINE_A)

#define  VRR_FLIPLINE_MASK			REG_GENMASK(19, 0)



#define _TRANS_VRR_STATUS2_A		0x6043C

#define _TRANS_VRR_STATUS2_B		0x6143C

#define _TRANS_VRR_STATUS2_C		0x6243C

#define _TRANS_VRR_STATUS2_D		0x6343C

#define _TRANS_VRR_STATUS2_A			0x6043c

#define _TRANS_VRR_STATUS2_B			0x6143c

#define _TRANS_VRR_STATUS2_C			0x6243c

#define _TRANS_VRR_STATUS2_D			0x6343c

#define TRANS_VRR_STATUS2(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)

#define  VRR_STATUS2_VERT_LN_CNT_MASK		REG_GENMASK(19, 0)



#define _TRANS_PUSH_A			0x60A70

#define _TRANS_PUSH_B			0x61A70

#define _TRANS_PUSH_C			0x62A70

#define _TRANS_PUSH_D			0x63A70

#define _TRANS_PUSH_A				0x60a70

#define _TRANS_PUSH_B				0x61a70

#define _TRANS_PUSH_C				0x62a70

#define _TRANS_PUSH_D				0x63a70

#define TRANS_PUSH(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)

#define  TRANS_PUSH_EN				REG_BIT(31)

#define  TRANS_PUSH_SEND			REG_BIT(30)