Commit fc9a7d38 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/enumeration'

- Allow 'isolated PCI functions' (multi-function devices without a function
  0) for LoongArch, similar to s390 and jailhouse (Huacai Chen)

- Mask out unrelated bits in PCIE_LNKCAP_SLS2SPEED() and
  PCIE_LNKCTL2_TLS2SPEED(), which makes them more robust and fixes a
  WARN_ON_ONCE() in pcie_set_target_speed() (Jiwei Sun)

- Read Link Control 2 again when retraining a link after a training failure
  so we try to increase the link speed (Jiwei Sun)

- Allow built-in drivers, not just modular drivers, to use async initial
  probing (Lukas Wunner)

- Support Immediate Readiness even on devices with no PM Capability (Sean
  Christopherson)

* pci/enumeration:
  PCI: Support Immediate Readiness on devices without PM capabilities
  PCI: Allow built-in drivers to use async initial probing
  PCI: Adjust the position of reading the Link Control 2 register
  PCI: Fix link speed calculation on retrain failure
  PCI: Extend isolated function probing to LoongArch
parents e6035a08 5c0d0ee3
Loading
Loading
Loading
Loading
+1 −4
Original line number Diff line number Diff line
@@ -341,7 +341,6 @@ void pci_bus_add_device(struct pci_dev *dev)
{
	struct device_node *dn = dev->dev.of_node;
	struct platform_device *pdev;
	int retval;

	/*
	 * Can not put in pci_device_add yet because resources
@@ -372,9 +371,7 @@ void pci_bus_add_device(struct pci_dev *dev)
	if (!dn || of_device_is_available(dn))
		pci_dev_allow_binding(dev);

	retval = device_attach(&dev->dev);
	if (retval < 0 && retval != -EPROBE_DEFER)
		pci_warn(dev, "device attach failed (%d)\n", retval);
	device_initial_probe(&dev->dev);

	pci_dev_assign_added(dev);
}
+0 −4
Original line number Diff line number Diff line
@@ -3205,7 +3205,6 @@ void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev)
void pci_pm_init(struct pci_dev *dev)
{
	int pm;
	u16 status;
	u16 pmc;

	device_enable_async_suspend(&dev->dev);
@@ -3266,9 +3265,6 @@ void pci_pm_init(struct pci_dev *dev)
		pci_pme_active(dev, false);
	}

	pci_read_config_word(dev, PCI_STATUS, &status);
	if (status & PCI_STATUS_IMM_READY)
		dev->imm_ready = 1;
	pci_pm_power_up_and_verify_state(dev);
	pm_runtime_forbid(&dev->dev);
	pm_runtime_set_active(&dev->dev);
+19 −13
Original line number Diff line number Diff line
@@ -391,12 +391,14 @@ void pci_bus_put(struct pci_bus *bus);

#define PCIE_LNKCAP_SLS2SPEED(lnkcap)					\
({									\
	((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :	\
	 (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT :	\
	 (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT :	\
	 (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT :	\
	 (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT :	\
	 (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT :	\
	u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS;			\
									\
	(lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :	\
	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT :	\
	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT :	\
	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT :	\
	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT :	\
	 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT :	\
	 PCI_SPEED_UNKNOWN);						\
})

@@ -411,13 +413,17 @@ void pci_bus_put(struct pci_bus *bus);
	 PCI_SPEED_UNKNOWN)

#define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \
	((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
	 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
	 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
	 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
	 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
	 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
	 PCI_SPEED_UNKNOWN)
({									\
	u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS;		\
									\
	(lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT :	\
	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT :	\
	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT :	\
	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT :	\
	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT :	\
	 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT :	\
	 PCI_SPEED_UNKNOWN);						\
})

/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
+10 −0
Original line number Diff line number Diff line
@@ -2595,6 +2595,15 @@ void pcie_report_downtraining(struct pci_dev *dev)
	__pcie_print_link_status(dev, false);
}

static void pci_imm_ready_init(struct pci_dev *dev)
{
	u16 status;

	pci_read_config_word(dev, PCI_STATUS, &status);
	if (status & PCI_STATUS_IMM_READY)
		dev->imm_ready = 1;
}

static void pci_init_capabilities(struct pci_dev *dev)
{
	pci_ea_init(dev);		/* Enhanced Allocation */
@@ -2604,6 +2613,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
	/* Buffers for saving PCIe and PCI-X capabilities */
	pci_allocate_cap_save_buffers(dev);

	pci_imm_ready_init(dev);	/* Immediate Readiness */
	pci_pm_init(dev);		/* Power Management */
	pci_vpd_init(dev);		/* Vital Product Data */
	pci_configure_ari(dev);		/* Alternative Routing-ID Forwarding */
+4 −2
Original line number Diff line number Diff line
@@ -105,13 +105,13 @@ int pcie_failed_link_retrain(struct pci_dev *dev)
	    !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting)
		return ret;

	pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2);
	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
	if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) {
		u16 oldlnkctl2 = lnkctl2;
		u16 oldlnkctl2;

		pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");

		pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2);
		ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false);
		if (ret) {
			pci_info(dev, "retraining failed\n");
@@ -123,6 +123,8 @@ int pcie_failed_link_retrain(struct pci_dev *dev)
		pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
	}

	pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2);

	if ((lnksta & PCI_EXP_LNKSTA_DLLLA) &&
	    (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT &&
	    pci_match_id(ids, dev)) {
Loading