Commit fd0bb2c7 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2024-02-06 (ixgbe)

This series contains updates to ixgbe driver only.

Jedrzej continues cleanup work from conversion away from ixgbe_status;
s32 values are changed to int, various style issues are addressed, and
some return statements refactored to address some smatch warnings.

* '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  ixgbe: Clarify the values of the returning status
  ixgbe: Rearrange args to fix reverse Christmas tree
  ixgbe: Convert ret val type from s32 to int
====================

Link: https://lore.kernel.org/r/20240206214054.1002919-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 458aabfd ef3dd596

drivers/net/ethernet/intel/ixgbe/ixgbe.h

+8 −8
Original line number Diff line number Diff line
@@ -949,19 +949,19 @@ void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 
void ixgbe_write_eitr(struct ixgbe_q_vector *);

int ixgbe_poll(struct napi_struct *napi, int budget);

int ethtool_ioctl(struct ifreq *ifr);

s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);

s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);

s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);

s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,

int ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);

int ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);

int ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);

int ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,

					  union ixgbe_atr_hash_dword input,

					  union ixgbe_atr_hash_dword common,

					  u8 queue);

s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,

int ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,

				    union ixgbe_atr_input *input_mask);

s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,

int ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,

					  union ixgbe_atr_input *input,

					  u16 soft_id, u8 queue);

s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,

int ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,

					  union ixgbe_atr_input *input,

					  u16 soft_id);

void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
@@ -1059,7 +1059,7 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 
u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);

void ixgbe_store_key(struct ixgbe_adapter *adapter);

void ixgbe_store_reta(struct ixgbe_adapter *adapter);

s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,

int ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,

		       u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);

#ifdef CONFIG_IXGBE_IPSEC

void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+35 −35
Original line number Diff line number Diff line
@@ -15,10 +15,10 @@ 
#define IXGBE_82598_VFT_TBL_SIZE 128

#define IXGBE_82598_RX_PB_SIZE	 512



static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,

static int ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,

					 ixgbe_link_speed speed,

					 bool autoneg_wait_to_complete);

static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,

static int ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,

				       u8 *eeprom_data);



/**
@@ -66,7 +66,7 @@ static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 
	IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);

}



static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)

static int ixgbe_get_invariants_82598(struct ixgbe_hw *hw)

{

	struct ixgbe_mac_info *mac = &hw->mac;
@@ -93,12 +93,12 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 
 *  not known.  Perform the SFP init if necessary.

 *

 **/

static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)

static int ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)

{

	struct ixgbe_mac_info *mac = &hw->mac;

	struct ixgbe_phy_info *phy = &hw->phy;

	s32 ret_val;

	u16 list_offset, data_offset;

	int ret_val;



	/* Identify the PHY */

	phy->ops.identify(hw);
@@ -148,9 +148,9 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 
 *  Then set pcie completion timeout

 *

 **/

static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)

static int ixgbe_start_hw_82598(struct ixgbe_hw *hw)

{

	s32 ret_val;

	int ret_val;



	ret_val = ixgbe_start_hw_generic(hw);

	if (ret_val)
@@ -170,7 +170,7 @@ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 
 *

 *  Determines the link capabilities by reading the AUTOC register.

 **/

static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,

static int ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,

					     ixgbe_link_speed *speed,

					     bool *autoneg)

{
@@ -271,7 +271,7 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 
 *

 *  Enable flow control according to the current settings.

 **/

static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)

static int ixgbe_fc_enable_82598(struct ixgbe_hw *hw)

{

	u32 fctrl_reg;

	u32 rmcs_reg;
@@ -411,13 +411,13 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 
 *  Configures link settings based on values in the ixgbe_hw struct.

 *  Restarts the link.  Performs autonegotiation if needed.

 **/

static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,

static int ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,

				      bool autoneg_wait_to_complete)

{

	int status = 0;

	u32 autoc_reg;

	u32 links_reg;

	u32 i;

	s32 status = 0;



	/* Restart link */

	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
@@ -457,7 +457,7 @@ static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 
 *  Function indicates success when phy link is available. If phy is not ready

 *  within 5 seconds of MAC indicating link, the function returns error.

 **/

static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)

static int ixgbe_validate_link_ready(struct ixgbe_hw *hw)

{

	u32 timeout;

	u16 an_reg;
@@ -493,7 +493,7 @@ static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 
 *

 *  Reads the links register to determine if link is up and the current speed

 **/

static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,

static int ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,

				      ixgbe_link_speed *speed, bool *link_up,

				      bool link_up_wait_to_complete)

{
@@ -579,7 +579,7 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 
 *

 *  Set the link speed in the AUTOC register and restarts link.

 **/

static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,

static int ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,

				      ixgbe_link_speed speed,

				      bool autoneg_wait_to_complete)

{
@@ -624,11 +624,11 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 
 *

 *  Sets the link speed in the AUTOC register in the MAC and restarts link.

 **/

static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,

static int ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,

					 ixgbe_link_speed speed,

					 bool autoneg_wait_to_complete)

{

	s32 status;

	int status;



	/* Setup the PHY according to input speed */

	status = hw->phy.ops.setup_link_speed(hw, speed,
@@ -647,15 +647,15 @@ static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 
 *  clears all interrupts, performing a PHY reset, and performing a link (MAC)

 *  reset.

 **/

static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)

static int ixgbe_reset_hw_82598(struct ixgbe_hw *hw)

{

	s32 status;

	s32 phy_status = 0;

	u32 ctrl;

	int phy_status = 0;

	u8  analog_val;

	u32 gheccr;

	u32 i;

	int status;

	u32 autoc;

	u8  analog_val;

	u32 ctrl;

	u32 i;



	/* Call adapter stop to disable tx/rx and clear interrupts */

	status = hw->mac.ops.stop_adapter(hw);
@@ -781,7 +781,7 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 
 *  @rar: receive address register index to associate with a VMDq index

 *  @vmdq: VMDq set index

 **/

static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

static int ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

{

	u32 rar_high;

	u32 rar_entries = hw->mac.num_rar_entries;
@@ -805,7 +805,7 @@ static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 
 *  @rar: receive address register index to associate with a VMDq index

 *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)

 **/

static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

static int ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

{

	u32 rar_high;

	u32 rar_entries = hw->mac.num_rar_entries;
@@ -836,7 +836,7 @@ static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 
 *

 *  Turn on/off specified VLAN in the VLAN filter table.

 **/

static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,

static int ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,

				bool vlan_on, bool vlvf_bypass)

{

	u32 regindex;
@@ -881,7 +881,7 @@ static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 
 *

 *  Clears the VLAN filter table, and the VMDq index associated with the filter

 **/

static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)

static int ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)

{

	u32 offset;

	u32 vlanbyte;
@@ -905,7 +905,7 @@ static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 
 *

 *  Performs read operation to Atlas analog register specified.

 **/

static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)

static int ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)

{

	u32  atlas_ctl;
@@ -927,7 +927,7 @@ static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 
 *

 *  Performs write operation to Atlas analog register specified.

 **/

static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)

static int ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)

{

	u32  atlas_ctl;
@@ -948,13 +948,13 @@ static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 
 *

 *  Performs 8 byte read operation to SFP module's data over I2C interface.

 **/

static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,

static int ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,

				    u8 byte_offset, u8 *eeprom_data)

{

	s32 status = 0;

	u16 sfp_addr = 0;

	u16 sfp_data = 0;

	u16 sfp_stat = 0;

	int status = 0;

	u16 gssr;

	u32 i;
@@ -1019,7 +1019,7 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, 
 *

 *  Performs 8 byte read operation to SFP module's EEPROM over I2C interface.

 **/

static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,

static int ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,

				       u8 *eeprom_data)

{

	return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
@@ -1034,7 +1034,7 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 
 *

 *  Performs 8 byte read operation to SFP module's SFF-8472 data over I2C

 **/

static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,

static int ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,

					u8 *sff8472_data)

{

	return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+76 −75
Original line number Diff line number Diff line
@@ -21,24 +21,24 @@ static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 
static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);

static void

ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed);

static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,

static int ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,

					   ixgbe_link_speed speed,

					   bool autoneg_wait_to_complete);

static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);

static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,

static int ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,

				      bool autoneg_wait_to_complete);

static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,

static int ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,

				      ixgbe_link_speed speed,

				      bool autoneg_wait_to_complete);

static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,

static int ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,

					 ixgbe_link_speed speed,

					 bool autoneg_wait_to_complete);

static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);

static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

static int ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);

static int ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

				     u8 dev_addr, u8 *data);

static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

static int ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

				      u8 dev_addr, u8 data);

static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);

static int ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);

static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);



bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
@@ -98,10 +98,10 @@ static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 
	}

}



static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)

static int ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)

{

	s32 ret_val;

	u16 list_offset, data_offset, data_value;

	int ret_val;



	if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {

		ixgbe_init_mac_link_ops_82599(hw);
@@ -173,10 +173,10 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 
 *  prot_autoc_write_82599().  Note, that locked can only be true in cases

 *  where this function doesn't return an error.

 **/

static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,

static int prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,

				 u32 *reg_val)

{

	s32 ret_val;

	int ret_val;



	*locked = false;

	/* If LESM is on then we need to hold the SW/FW semaphore. */
@@ -203,9 +203,9 @@ static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, 
 * This part (82599) may need to hold a the SW/FW lock around all writes to

 * AUTOC. Likewise after a write we need to do a pipeline reset.

 **/

static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)

static int prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)

{

	s32 ret_val = 0;

	int ret_val = 0;



	/* Blocked by MNG FW so bail */

	if (ixgbe_check_reset_blocked(hw))
@@ -237,7 +237,7 @@ static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 
	return ret_val;

}



static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)

static int ixgbe_get_invariants_82599(struct ixgbe_hw *hw)

{

	struct ixgbe_mac_info *mac = &hw->mac;
@@ -263,11 +263,11 @@ static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 
 *  not known.  Perform the SFP init if necessary.

 *

 **/

static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)

static int ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)

{

	struct ixgbe_mac_info *mac = &hw->mac;

	struct ixgbe_phy_info *phy = &hw->phy;

	s32 ret_val;

	int ret_val;

	u32 esdp;



	if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
@@ -322,7 +322,7 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 
 *

 *  Determines the link capabilities by reading the AUTOC register.

 **/

static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,

static int ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,

					     ixgbe_link_speed *speed,

					     bool *autoneg)

{
@@ -500,14 +500,14 @@ static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 
 *  Configures link settings based on values in the ixgbe_hw struct.

 *  Restarts the link.  Performs autonegotiation if needed.

 **/

static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,

static int ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,

				      bool autoneg_wait_to_complete)

{

	bool got_lock = false;

	int status = 0;

	u32 autoc_reg;

	u32 links_reg;

	u32 i;

	s32 status = 0;

	bool got_lock = false;



	if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {

		status = hw->mac.ops.acquire_swfw_sync(hw,
@@ -657,15 +657,15 @@ ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 
 *

 *  Implements the Intel SmartSpeed algorithm.

 **/

static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,

static int ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,

					   ixgbe_link_speed speed,

					   bool autoneg_wait_to_complete)

{

	s32 status = 0;

	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;

	s32 i, j;

	bool link_up = false;

	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);

	bool link_up = false;

	int status = 0;

	s32 i, j;



	 /* Set autoneg_advertised value based on input link speed */

	hw->phy.autoneg_advertised = 0;
@@ -767,16 +767,15 @@ static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 
 *

 *  Set the link speed in the AUTOC register and restarts link.

 **/

static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,

static int ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,

				      ixgbe_link_speed speed,

				      bool autoneg_wait_to_complete)

{

	bool autoneg = false;

	s32 status;

	u32 pma_pmd_1g, link_mode, links_reg, i;

	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;

	ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;

	u32 pma_pmd_10g_serial, pma_pmd_1g, link_mode, links_reg, i;

	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

	bool autoneg = false;

	int status;



	/* holds the value of AUTOC register at this current point in time */

	u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
@@ -785,6 +784,8 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 
	/* temporary variable used for comparison purposes */

	u32 autoc = current_autoc;



	pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;



	/* Check to see if speed passed in is supported. */

	status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,

						   &autoneg);
@@ -882,11 +883,11 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 
 *

 *  Restarts link on PHY and MAC based on settings passed in.

 **/

static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,

static int ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,

					 ixgbe_link_speed speed,

					 bool autoneg_wait_to_complete)

{

	s32 status;

	int status;



	/* Setup the PHY according to input speed */

	status = hw->phy.ops.setup_link_speed(hw, speed,
@@ -905,13 +906,13 @@ static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 
 *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)

 *  reset.

 **/

static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)

static int ixgbe_reset_hw_82599(struct ixgbe_hw *hw)

{

	ixgbe_link_speed link_speed;

	s32 status;

	u32 ctrl, i, autoc, autoc2;

	u32 curr_lms;

	bool link_up = false;

	u32 curr_lms;

	int status;



	/* Call adapter stop to disable tx/rx and clear interrupts */

	status = hw->mac.ops.stop_adapter(hw);
@@ -1081,7 +1082,7 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 
 * @hw: pointer to hardware structure

 * @fdircmd: current value of FDIRCMD register

 */

static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)

static int ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)

{

	int i;
@@ -1099,12 +1100,12 @@ static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 
 *  ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.

 *  @hw: pointer to hardware structure

 **/

s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)

int ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)

{

	int i;

	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);

	u32 fdircmd;

	s32 err;

	int err;

	int i;



	fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
@@ -1212,7 +1213,7 @@ static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 
 *  @fdirctrl: value to write to flow director control register, initially

 *             contains just the value of the Rx packet buffer allocation

 **/

s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)

int ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)

{

	/*

	 * Continue setup of fdirctrl register bits:
@@ -1236,7 +1237,7 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 
 *  @fdirctrl: value to write to flow director control register, initially

 *             contains just the value of the Rx packet buffer allocation

 **/

s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)

int ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)

{

	/*

	 * Continue setup of fdirctrl register bits:
@@ -1359,7 +1360,7 @@ static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 
 * Note that the tunnel bit in input must not be set when the hardware

 * tunneling support does not exist.

 **/

s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,

int ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,

					  union ixgbe_atr_hash_dword input,

					  union ixgbe_atr_hash_dword common,

					  u8 queue)
@@ -1515,7 +1516,7 @@ static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 


#define IXGBE_STORE_AS_BE16(_value) __swab16(ntohs((_value)))



s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,

int ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,

				    union ixgbe_atr_input *input_mask)

{

	/* mask IPv6 since it is currently not supported */
@@ -1627,12 +1628,12 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 
	return 0;

}



s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,

int ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,

					  union ixgbe_atr_input *input,

					  u16 soft_id, u8 queue)

{

	u32 fdirport, fdirvlan, fdirhash, fdircmd;

	s32 err;

	int err;



	/* currently IPv6 is not supported, must be programmed with 0 */

	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
@@ -1690,13 +1691,13 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 
	return 0;

}



s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,

int ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,

					  union ixgbe_atr_input *input,

					  u16 soft_id)

{

	u32 fdirhash;

	u32 fdircmd;

	s32 err;

	int err;



	/* configure FDIRHASH register */

	fdirhash = (__force u32)input->formatted.bkt_hash;
@@ -1734,7 +1735,7 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 
 *

 *  Performs read operation to Omer analog register specified.

 **/

static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)

static int ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)

{

	u32  core_ctl;
@@ -1756,7 +1757,7 @@ static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 
 *

 *  Performs write operation to Omer analog register specified.

 **/

static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)

static int ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)

{

	u32  core_ctl;
@@ -1776,9 +1777,9 @@ static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 
 *  and the generation start_hw function.

 *  Then performs revision-specific operations, if any.

 **/

static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)

static int ixgbe_start_hw_82599(struct ixgbe_hw *hw)

{

	s32 ret_val = 0;

	int ret_val = 0;



	ret_val = ixgbe_start_hw_generic(hw);

	if (ret_val)
@@ -1802,9 +1803,9 @@ static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 
 *  If PHY already detected, maintains current PHY type in hw struct,

 *  otherwise executes the PHY detection routine.

 **/

static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)

static int ixgbe_identify_phy_82599(struct ixgbe_hw *hw)

{

	s32 status;

	int status;



	/* Detect PHY if not unknown - returns success if already detected. */

	status = ixgbe_identify_phy_generic(hw);
@@ -1835,7 +1836,7 @@ static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 
 *

 *  Enables the Rx DMA unit for 82599

 **/

static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)

static int ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)

{

	/*

	 * Workaround for 82599 silicon errata when enabling the Rx datapath.
@@ -1865,12 +1866,12 @@ static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 
 *  Return: -EACCES if the FW is not present or if the FW version is

 *  not supported.

 **/

static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)

static int ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)

{

	u16 fw_offset, fw_ptp_cfg_offset;

	s32 status = -EACCES;

	u16 offset;

	int status = -EACCES;

	u16 fw_version = 0;

	u16 offset;



	/* firmware check is only necessary for SFI devices */

	if (hw->phy.media_type != ixgbe_media_type_fiber)
@@ -1917,7 +1918,7 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 
static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)

{

	u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;

	s32 status;

	int status;



	/* get the offset to the Firmware Module block */

	status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
@@ -1956,7 +1957,7 @@ static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 
 *

 *  Retrieves 16 bit word(s) read from EEPROM

 **/

static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,

static int ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,

					  u16 words, u16 *data)

{

	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
@@ -1982,7 +1983,7 @@ static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 
 *

 *  Reads a 16 bit word from the EEPROM

 **/

static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,

static int ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,

				   u16 offset, u16 *data)

{

	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
@@ -2006,11 +2007,11 @@ static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 
 * full pipeline reset.  Note - We must hold the SW/FW semaphore before writing

 * to AUTOC, so this function assumes the semaphore is held.

 **/

static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)

static int ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)

{

	s32 ret_val;

	u32 anlp1_reg = 0;

	u32 i, autoc_reg, autoc2_reg;

	u32 anlp1_reg = 0;

	int ret_val;



	/* Enable link if disabled in NVM */

	autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
@@ -2061,12 +2062,12 @@ static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 
 *  Performs byte read operation to SFP module's EEPROM over I2C interface at

 *  a specified device address.

 **/

static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

static int ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

				     u8 dev_addr, u8 *data)

{

	u32 esdp;

	s32 status;

	s32 timeout = 200;

	int status;

	u32 esdp;



	if (hw->phy.qsfp_shared_i2c_bus == true) {

		/* Acquire I2C bus ownership. */
@@ -2115,12 +2116,12 @@ static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 
 *  Performs byte write operation to SFP module's EEPROM over I2C interface at

 *  a specified device address.

 **/

static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

static int ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

				      u8 dev_addr, u8 data)

{

	u32 esdp;

	s32 status;

	s32 timeout = 200;

	int status;

	u32 esdp;



	if (hw->phy.qsfp_shared_i2c_bus == true) {

		/* Acquire I2C bus ownership. */

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+131 −131

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

+56 −56
Original line number Diff line number Diff line
@@ -8,89 +8,89 @@ 
#include "ixgbe.h"



u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);

s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);

s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);

s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);

s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);

s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,

int ixgbe_init_hw_generic(struct ixgbe_hw *hw);

int ixgbe_start_hw_generic(struct ixgbe_hw *hw);

int ixgbe_start_hw_gen2(struct ixgbe_hw *hw);

int ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);

int ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,

				  u32 pba_num_size);

s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);

int ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);

enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status);

enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status);

s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);

int ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);

void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);

s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);

int ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);



s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);

s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);

s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw);

int ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);

int ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);

int ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw);



s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);

s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);

s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,

int ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);

int ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);

int ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,

					       u16 words, u16 *data);

s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);

s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,

int ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);

int ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,

				   u16 words, u16 *data);

s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);

s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,

int ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);

int ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,

				    u16 words, u16 *data);

s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,

int ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,

				       u16 *data);

s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,

int ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,

					      u16 words, u16 *data);

s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);

s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,

int ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);

int ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,

					   u16 *checksum_val);

s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);

int ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);



s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

int ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

			  u32 enable_addr);

s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);

s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);

s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,

int ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);

int ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);

int ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,

				      struct net_device *netdev);

s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);

s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);

s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw);

s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);

s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);

s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);

s32 ixgbe_setup_fc_generic(struct ixgbe_hw *);

int ixgbe_enable_mc_generic(struct ixgbe_hw *hw);

int ixgbe_disable_mc_generic(struct ixgbe_hw *hw);

int ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw);

int ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);

int ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);

int ixgbe_fc_enable_generic(struct ixgbe_hw *hw);

int ixgbe_setup_fc_generic(struct ixgbe_hw *);

bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);

void ixgbe_fc_autoneg(struct ixgbe_hw *hw);



s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);

int ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);

void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);

s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);

s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);

s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);

s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,

int ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);

int ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

int ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);

int ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

int ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);

int ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,

			   u32 vind, bool vlan_on, bool vlvf_bypass);

s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);

s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,

int ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);

int ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,

				 ixgbe_link_speed *speed,

				 bool *link_up, bool link_up_wait_to_complete);

s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,

int ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,

				 u16 *wwpn_prefix);



s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);

s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);

int prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);

int prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);



s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);

s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);

int ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);

int ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);

void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);

void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);

s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);

s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,

int ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);

int ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,

				 u8 build, u8 ver, u16 len, const char *str);

u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);

s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length,

int ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length,

				 u32 timeout, bool return_data);

s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 len, u32 timeout);

s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,

int ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 len, u32 timeout);

int ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,

			  u32 (*data)[FW_PHY_ACT_DATA_COUNT]);

void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);

bool ixgbe_mng_present(struct ixgbe_hw *hw);
@@ -111,8 +111,8 @@ extern const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT]; 
#define IXGBE_EMC_DIODE3_DATA		0x2A

#define IXGBE_EMC_DIODE3_THERM_LIMIT	0x30



s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);

s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);

int ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);

int ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);

void ixgbe_get_etk_id(struct ixgbe_hw *hw,

		      struct ixgbe_nvm_version *nvm_ver);

void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
@@ -121,7 +121,7 @@ void ixgbe_get_orom_version(struct ixgbe_hw *hw, 
			    struct ixgbe_nvm_version *nvm_ver);

void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);

void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);

s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,

int ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,

					  ixgbe_link_speed speed,

					  bool autoneg_wait_to_complete);

void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,