Commit fd3fece0 authored by Kaier Hsueg's avatar Kaier Hsueg Committed by Alex Deucher
Browse files

drm/amd/display: Fix P010, NV12, YUY2 scale down by four times failure 



[WHY]
When performing 4:1 downscaling with subsampled formats,
the SPL remainder distribution logic (+1) overrides the
upper layer’s aligned width, resulting in odd segment
widths and causing hang.

The upper layer alignment ensures the width is sufficient
and even, so SPL should not modify it further.

[HOW]
In dc_spl.c within calculate_mpc_slice_in_timing_active,
add an extra condition: Skip the remainder distribution
(+1) when use_recout_width_aligned is true.This change
respects the upper layer’s alignment decision, prevents
odd widths, and is a minimal, safe fix.

Reviewed-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Signed-off-by: default avatarKaier Hsueh <Kaier.Hsueh@amd.com>
Signed-off-by: default avatarChenyu Chen <chen-yu.chen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent af330397

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

+2 −1
Original line number Diff line number Diff line
@@ -226,7 +226,8 @@ static struct spl_rect calculate_mpc_slice_in_timing_active( 
	/* extra pixels in the division remainder need to go to pipes after

	 * the extra pixel index minus one(epimo) defined here as:

	 */

	if (mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) {

	if ((use_recout_width_aligned == false) &&

		mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) {

		mpc_rec.x += mpc_slice_idx - epimo - 1;

		mpc_rec.width += 1;

	}