Commit fd7b48b1 authored by Anand Moon's avatar Anand Moon Committed by Neil Armstrong
Browse files

arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC 



As per S905X3 datasheet add missing cache information to the Amlogic
SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.

- Each Cortex-A55 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 256KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: default avatarAnand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-3-linux.amoon@gmail.com


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent d7fc05da

arch/arm64/boot/dts/amlogic/meson-sm1.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -55,6 +55,12 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x0>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};
@@ -64,6 +70,12 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x1>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};
@@ -73,6 +85,12 @@ cpu2: cpu@2 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x2>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};
@@ -82,6 +100,12 @@ cpu3: cpu@3 { 
			compatible = "arm,cortex-a55";

			reg = <0x0 0x3>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};
@@ -90,6 +114,9 @@ l2: l2-cache0 { 
			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x40000>; /* L2. 256 KB */

			cache-line-size = <64>;

			cache-sets = <256>;

		};

	};