Commit fd95e1b1 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: switch to ih_toggle_interrupts for vega10 



replace ih_enable_interrupts and ih_disable_interrupts
with ih_toggle_interrupts

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarDennis Li <Dennis.Li@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f0594717

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+34 −134
Original line number Diff line number Diff line
@@ -84,135 +84,6 @@ static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 
	}

}



/**

 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer

 *

 * @adev: amdgpu_device pointer

 *

 * Enable the interrupt ring buffer (VEGA10).

 */

static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)

{

	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);



	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

	if (amdgpu_sriov_vf(adev)) {

		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return;

		}

	} else {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}

	adev->irq.ih.enabled = true;



	if (adev->irq.ih1.ring_size) {

		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

					   RB_ENABLE, 1);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

		}

		adev->irq.ih1.enabled = true;

	}



	if (adev->irq.ih2.ring_size) {

		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,

					   RB_ENABLE, 1);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);

		}

		adev->irq.ih2.enabled = true;

	}



	if (adev->irq.ih_soft.ring_size)

		adev->irq.ih_soft.enabled = true;

}



/**

 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer

 *

 * @adev: amdgpu_device pointer

 *

 * Disable the interrupt ring buffer (VEGA10).

 */

static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)

{

	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);



	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

	if (amdgpu_sriov_vf(adev)) {

		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return;

		}

	} else {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}



	/* set rptr, wptr to 0 */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);

	adev->irq.ih.enabled = false;

	adev->irq.ih.rptr = 0;



	if (adev->irq.ih1.ring_size) {

		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

					   RB_ENABLE, 0);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

		}

		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);

		adev->irq.ih1.enabled = false;

		adev->irq.ih1.rptr = 0;

	}



	if (adev->irq.ih2.ring_size) {

		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,

					   RB_ENABLE, 0);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);

		}



		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);

		adev->irq.ih2.enabled = false;

		adev->irq.ih2.rptr = 0;

	}

}



/**

 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer

 *
@@ -258,6 +129,31 @@ static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 
	return 0;

}



/**

 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers

 *

 * @adev: amdgpu_device pointer

 * @enable: enable or disable interrupt ring buffers

 *

 * Toggle all the available interrupt ring buffers (VEGA10).

 */

static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)

{

	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};

	int i;

	int r;



	for (i = 0; i < ARRAY_SIZE(ih); i++) {

		if (ih[i]->ring_size) {

			r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable);

			if (r)

				return r;

		}

	}



	return 0;

}



static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)

{

	int rb_bufsz = order_base_2(ih->ring_size / 4);
@@ -367,11 +263,13 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
{

	struct amdgpu_ih_ring *ih;

	u32 ih_rb_cntl, ih_chicken;

	int ret = 0;

	int ret;

	u32 tmp;



	/* disable irqs */

	vega10_ih_disable_interrupts(adev);

	ret = vega10_ih_toggle_interrupts(adev, false);

	if (ret)

		return ret;



	adev->nbio.funcs->ih_control(adev);
@@ -489,9 +387,11 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
	pci_set_master(adev->pdev);



	/* enable interrupts */

	vega10_ih_enable_interrupts(adev);



	ret = vega10_ih_toggle_interrupts(adev, true);

	if (ret)

		return ret;



	return 0;

}



/**
@@ -503,7 +403,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
 */

static void vega10_ih_irq_disable(struct amdgpu_device *adev)

{

	vega10_ih_disable_interrupts(adev);

	vega10_ih_toggle_interrupts(adev, false);



	/* Wait and acknowledge irq */

	mdelay(1);