Commit fd9809ec authored by Huan He's avatar Huan He Committed by Ulf Hansson
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mmc: sdhci-of-dwcmshc: Fix init for AXI clock for Eswin EIC7700 



Accessing the High-Speed registers requires the AXI clock to be enabled.

Signed-off-by: default avatarHuan He <hehuan1@eswincomputing.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Fixes: 32b26332 ("mmc: sdhci-of-dwcmshc: Add support for Eswin EIC7700")
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 12261022

drivers/mmc/host/sdhci-of-dwcmshc.c

+6 −0
Original line number Diff line number Diff line
@@ -1595,6 +1595,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm 
{

	u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;

	unsigned int val, hsp_int_status, hsp_pwr_ctrl;

	static const char * const clk_ids[] = {"axi"};

	struct of_phandle_args args;

	struct eic7700_priv *priv;

	struct regmap *hsp_regmap;
@@ -1612,6 +1613,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm 
		return ret;

	}



	ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,

					    ARRAY_SIZE(clk_ids), clk_ids);

	if (ret)

		return ret;



	ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args);

	if (ret) {

		dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret);