Commit fdcb4f10 authored by Justin Swartz's avatar Justin Swartz Committed by Thomas Bogendoerfer
Browse files

mips: dts: ralink: mt7621: reorder pcie node attributes and children 



Reorder the attributes and child nodes of the PCIe Controller
node to meet the DTS style guidelines.

Signed-off-by: default avatarJustin Swartz <justin.swartz@risingedge.co.za>
Reviewed-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 6f04e524

arch/mips/boot/dts/ralink/mt7621.dtsi

+43 −25
Original line number Diff line number Diff line
@@ -495,70 +495,88 @@ pcie: pcie@1e140000 { 
		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */

		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */

		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */

		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */

			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */



		#address-cells = <3>;

		#interrupt-cells = <1>;

		#size-cells = <2>;



		pinctrl-names = "default";

		pinctrl-0 = <&pcie_pins>;



		device_type = "pci";



		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */

			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */



		#interrupt-cells = <1>;

		interrupt-map-mask = <0xF800 0 0 0>;

		interrupt-map-mask = <0xf800 0 0 0>;

		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED  4 IRQ_TYPE_LEVEL_HIGH>,

				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,

				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;



		status = "disabled";

		pinctrl-names = "default";

		pinctrl-0 = <&pcie_pins>;



		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;



		status = "disabled";



		pcie@0,0 {

			reg = <0x0000 0 0 0 0>;

			ranges;



			#address-cells = <3>;

			#interrupt-cells = <1>;

			#size-cells = <2>;



			clocks = <&sysc MT7621_CLK_PCIE0>;



			device_type = "pci";

			#interrupt-cells = <1>;



			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&sysc MT7621_RST_PCIE0>;

			clocks = <&sysc MT7621_CLK_PCIE0>;

			phys = <&pcie0_phy 1>;



			phy-names = "pcie-phy0";

			ranges;

			phys = <&pcie0_phy 1>;



			resets = <&sysc MT7621_RST_PCIE0>;

		};



		pcie@1,0 {

			reg = <0x0800 0 0 0 0>;

			ranges;



			#address-cells = <3>;

			#interrupt-cells = <1>;

			#size-cells = <2>;



			clocks = <&sysc MT7621_CLK_PCIE1>;



			device_type = "pci";

			#interrupt-cells = <1>;



			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&sysc MT7621_RST_PCIE1>;

			clocks = <&sysc MT7621_CLK_PCIE1>;

			phys = <&pcie0_phy 1>;



			phy-names = "pcie-phy1";

			ranges;

			phys = <&pcie0_phy 1>;



			resets = <&sysc MT7621_RST_PCIE1>;

		};



		pcie@2,0 {

			reg = <0x1000 0 0 0 0>;

			ranges;



			#address-cells = <3>;

			#interrupt-cells = <1>;

			#size-cells = <2>;



			clocks = <&sysc MT7621_CLK_PCIE2>;



			device_type = "pci";

			#interrupt-cells = <1>;



			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&sysc MT7621_RST_PCIE2>;

			clocks = <&sysc MT7621_CLK_PCIE2>;

			phys = <&pcie2_phy 0>;



			phy-names = "pcie-phy2";

			ranges;

			phys = <&pcie2_phy 0>;



			resets = <&sysc MT7621_RST_PCIE2>;

		};

	};