Commit fe4e9ff9 authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu: add mc wptr addr support for mes 



MES requires mc wptr address for usermode queues.
Export bo gart address for mc wptr address.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ca0cb895

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+8 −2
Original line number Diff line number Diff line
@@ -675,6 +675,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 
	queue_input.doorbell_offset = qprops->doorbell_off;

	queue_input.mqd_addr = queue->mqd_gpu_addr;

	queue_input.wptr_addr = qprops->wptr_gpu_addr;

	queue_input.wptr_mc_addr = qprops->wptr_mc_addr;

	queue_input.queue_type = qprops->queue_type;

	queue_input.paging = qprops->paging;

	queue_input.is_kfd_process = 0;
@@ -802,6 +803,8 @@ amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev, 
	props->hqd_base_gpu_addr = ring->gpu_addr;

	props->rptr_gpu_addr = ring->rptr_gpu_addr;

	props->wptr_gpu_addr = ring->wptr_gpu_addr;

	props->wptr_mc_addr =

		ring->mes_ctx->meta_data_mc_addr + ring->wptr_offs;

	props->queue_size = ring->ring_size;

	props->eop_gpu_addr = ring->eop_gpu_addr;

	props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;
@@ -962,7 +965,8 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 
	r = amdgpu_bo_create_kernel(adev,

			    sizeof(struct amdgpu_mes_ctx_meta_data),

			    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,

			    &ctx_data->meta_data_obj, NULL,

			    &ctx_data->meta_data_obj,

			    &ctx_data->meta_data_mc_addr,

			    &ctx_data->meta_data_ptr);

	if (!ctx_data->meta_data_obj)

		return -ENOMEM;
@@ -976,7 +980,9 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 
void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data)

{

	if (ctx_data->meta_data_obj)

		amdgpu_bo_free_kernel(&ctx_data->meta_data_obj, NULL, NULL);

		amdgpu_bo_free_kernel(&ctx_data->meta_data_obj,

				      &ctx_data->meta_data_mc_addr,

				      &ctx_data->meta_data_ptr);

}



int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+2 −0
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ struct amdgpu_mes_queue_properties { 
	uint64_t                hqd_base_gpu_addr;

	uint64_t                rptr_gpu_addr;

	uint64_t                wptr_gpu_addr;

	uint64_t                wptr_mc_addr;

	uint32_t                queue_size;

	uint64_t                eop_gpu_addr;

	uint32_t                hqd_pipe_priority;
@@ -208,6 +209,7 @@ struct mes_add_queue_input { 
	uint32_t	doorbell_offset;

	uint64_t	mqd_addr;

	uint64_t	wptr_addr;

	uint64_t	wptr_mc_addr;

	uint32_t	queue_type;

	uint32_t	paging;

	uint32_t        gws_base;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ struct amdgpu_mes_ctx_meta_data { 
struct amdgpu_mes_ctx_data {

	struct amdgpu_bo	*meta_data_obj;

	uint64_t                meta_data_gpu_addr;

	uint64_t                meta_data_mc_addr;

	struct amdgpu_bo_va	*meta_data_va;

	void                    *meta_data_ptr;

	uint32_t                gang_ids[AMDGPU_HW_IP_DMA+1];

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+7 −1
Original line number Diff line number Diff line
@@ -156,7 +156,13 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 
		input->gang_global_priority_level;

	mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;

	mes_add_queue_pkt.mqd_addr = input->mqd_addr;



	if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>

			AMDGPU_MES_API_VERSION_SHIFT) >= 2)

		mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;

	else

		mes_add_queue_pkt.wptr_addr = input->wptr_addr;



	mes_add_queue_pkt.queue_type =

		convert_to_mes_queue_type(input->queue_type);

	mes_add_queue_pkt.paging = input->paging;

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

+3 −3
Original line number Diff line number Diff line
@@ -197,12 +197,12 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, 
					AMDGPU_MES_PRIORITY_LEVEL_NORMAL;

	queue_input.doorbell_offset = q->properties.doorbell_off;

	queue_input.mqd_addr = q->gart_mqd_addr;

	queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;



	if (q->wptr_bo) {

		wptr_addr_off = (uint64_t)q->properties.write_ptr - (uint64_t)q->wptr_bo->kfd_bo->va;

		queue_input.wptr_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;

	} else

		queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;

		queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;

	}



	queue_input.is_kfd_process = 1;