Commit fea58424 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 



Add the missing port pins P19 to P28 for RZ/Five SoC. These additional
pins provide expanded capabilities and are exclusive to the RZ/Five SoC.

Couple of port pins have different configuration and are not identical for
the complete port so introduce struct rzg2l_variable_pin_cfg to handle
such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config
is then assigned in rzg2l_pinctrl_get_variable_pin_cfg().

Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins
which support interrupt facility.

While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK().

Update the gpio-ranges property in the RZ/Five SoC DTSI, as it must
match the driver.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240129135556.63466-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 15e4ae4f

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -46,6 +46,10 @@ cpu0_intc: interrupt-controller { 
	};

};



&pinctrl {

	gpio-ranges = <&pinctrl 0 0 232>;

};



&soc {

	dma-noncoherent;

	interrupt-parent = <&plic>;

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+204 −9
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ 
#define PIN_CFG_IOLH_C			BIT(13)

#define PIN_CFG_SOFT_PS			BIT(14)

#define PIN_CFG_OEN			BIT(15)

#define PIN_CFG_VARIABLE		BIT(16)

#define PIN_CFG_NOGPIO_INT		BIT(17)



#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \

					(PIN_CFG_IOLH_##group | \
@@ -76,18 +78,24 @@ 
					 PIN_CFG_FILNUM | \

					 PIN_CFG_FILCLKSEL)



/*

 * n indicates number of pins in the port, a is the register index

 * and f is pin configuration capabilities supported.

 */

#define PIN_CFG_PIN_MAP_MASK		GENMASK_ULL(35, 28)

#define PIN_CFG_PIN_REG_MASK		GENMASK(27, 20)

#define PIN_CFG_MASK			GENMASK(19, 0)



#define RZG2L_GPIO_PORT_PACK(n, a, f)	((((1ULL << (n)) - 1) << 28) | \

/*

 * m indicates the bitmap of supported pins, a is the register index

 * and f is pin configuration capabilities supported.

 */

#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f)	(FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \

						 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \

						 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))



/*

 * n indicates number of pins in the port, a is the register index

 * and f is pin configuration capabilities supported.

 */

#define RZG2L_GPIO_PORT_PACK(n, a, f)	RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))



/*

 * BIT(63) indicates dedicated pin, p is the register index while

 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
@@ -199,6 +207,18 @@ struct rzg2l_dedicated_configs { 
	u64 config;

};



/**

 * struct rzg2l_variable_pin_cfg - pin data cfg

 * @cfg: port pin configuration

 * @port: port number

 * @pin: port pin

 */

struct rzg2l_variable_pin_cfg {

	u32 cfg:20;

	u32 port:5;

	u32 pin:3;

};



struct rzg2l_pinctrl_data {

	const char * const *port_pins;

	const u64 *port_pin_configs;
@@ -207,6 +227,8 @@ struct rzg2l_pinctrl_data { 
	unsigned int n_port_pins;

	unsigned int n_dedicated_pins;

	const struct rzg2l_hwcfg *hwcfg;

	const struct rzg2l_variable_pin_cfg *variable_pin_cfg;

	unsigned int n_variable_pin_cfg;

};



/**
@@ -242,6 +264,143 @@ struct rzg2l_pinctrl { 


static const u16 available_ps[] = { 1800, 2500, 3300 };



#ifdef CONFIG_RISCV

static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,

					      u64 pincfg,

					      unsigned int port,

					      u8 pin)

{

	unsigned int i;



	for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {

		if (pctrl->data->variable_pin_cfg[i].port == port &&

		    pctrl->data->variable_pin_cfg[i].pin == pin)

			return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg;

	}



	return 0;

}



static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = {

	{

		.port = 20,

		.pin = 0,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

		       PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 20,

		.pin = 1,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

		       PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 20,

		.pin = 2,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

		       PIN_CFG_IEN  | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 20,

		.pin = 3,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 20,

		.pin = 4,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 20,

		.pin = 5,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 20,

		.pin = 6,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 20,

		.pin = 7,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 23,

		.pin = 1,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT

	},

	{

		.port = 23,

		.pin = 2,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 23,

		.pin = 3,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 23,

		.pin = 4,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 23,

		.pin = 5,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 24,

		.pin = 0,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 24,

		.pin = 1,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 24,

		.pin = 2,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 24,

		.pin = 3,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 24,

		.pin = 4,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_NOGPIO_INT,

	},

	{

		.port = 24,

		.pin = 5,

		.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

		       PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

		       PIN_CFG_NOGPIO_INT,

	},

};

#endif



static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,

				       u8 pin, u8 off, u8 func)

{
@@ -1445,6 +1604,25 @@ static const u64 r9a07g043_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),

#ifdef CONFIG_RISCV

	/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */

	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

				    PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

				    PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),			/* P19 */

	RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE),				/* P20 */

	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

				    PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),			/* P21 */

	RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

			     PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),				/* P22 */

	RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE),			/* P23 */

	RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE),				/* P24 */

	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |

				    PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

				    PIN_CFG_NOGPIO_INT),				/* P25 */

	0x0,										/* P26 */

	0x0,										/* P27 */

	RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT),	/* P28 */

#endif

};



static const u64 r9a08g045_gpio_configs[] = {
@@ -1605,12 +1783,18 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 
						       PIN_CFG_IO_VMC_SD1)) },

};



static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)

static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)

{

	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];

	const struct rzg2l_pinctrl_data *data = pctrl->data;

	u64 *pin_data = pin_desc->drv_data;

	unsigned int gpioint;

	unsigned int i;

	u32 port, bit;



	if (*pin_data & PIN_CFG_NOGPIO_INT)

		return -EINVAL;



	port = virq / 8;

	bit = virq % 8;
@@ -1720,7 +1904,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 
	unsigned long flags;

	int gpioint, irq;



	gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);

	gpioint = rzg2l_gpio_get_gpioint(child, pctrl);

	if (gpioint < 0)

		return gpioint;
@@ -1906,6 +2090,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 
		if (i && !(i % RZG2L_PINS_PER_PORT))

			j++;

		pin_data[i] = pctrl->data->port_pin_configs[j];

#ifdef CONFIG_RISCV

		if (pin_data[i] & PIN_CFG_VARIABLE)

			pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,

									 pin_data[i],

									 j,

									 i % RZG2L_PINS_PER_PORT);

#endif

		pins[i].drv_data = &pin_data[i];

	}
@@ -2057,6 +2248,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { 
	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,

	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),

	.hwcfg = &rzg2l_hwcfg,

#ifdef CONFIG_RISCV

	.variable_pin_cfg = r9a07g043f_variable_pin_cfg,

	.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),

#endif

};



static struct rzg2l_pinctrl_data r9a07g044_data = {